SET and SEU simulation toolkit for LabVIEW

Nowadays, the fault simulation is an important step in any IC design. Predicting the behavioral faults of any process step is essential to ensure that the design is well implemented. During the simulation various problems can be detected and corrected. It is presented a tool to simulate the effects that occur when a source of fault is inserted in a digital circuit, especially SEU faults. To model a fault, it was also developed a TMR method capable of verifying the existence of a fault and to not let it spread through the whole circuit. It was also developed a Voltage Controlled Oscillator (VCO) to view fault effects in analog circuits. LabVIEW tool is used to create a set of virtual instruments to simulate SEUs. It is efficient in modeling the Characteristics of SETs. It is possible with this toolkit to replicate the effects of SEUs and SETs described in the literature.

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