New algorithms and VLSI architectures for SRT division and square root

Radix two algorithms for SRT division and square-rooting are developed. For these schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures for implementing the new division and square-rooting methods are also presented.<<ETX>>

[1]  Tomás Lang,et al.  On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.

[2]  N. Burgess.  A fast division algorithm for VLSI , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[3]  Tomás Lang,et al.  Fast radix-2 division with quotient-digit prediction , 1989 .

[4]  James E. Robertson,et al.  A New Class of Digital Division Methods , 1958, IRE Trans. Electron. Comput..

[5]  Naofumi Takagi,et al.  Design of high speed MOS multiplier and divider using redundant binary representation , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[6]  Chin Chin Tung.  A Division Algorithm for Signed-Digit Arithmetic , 1968, IEEE Transactions on Computers.

[7]  Daniel E. Atkins,et al.  Introduction to the Role of Redundancy in Computer Arithmetic , 1975, Computer.

[8]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[9]  Stanislaw Majerski.  Square-Rooting Algorithms for High-Speed Digital Circuits , 1985, IEEE Transactions on Computers.

[10]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[11]  P. Fortier,et al.  A very fast digital realization of a time-domain block LMS filter , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.