An integrated mapping table for hybrid FTL with fault-tolerant address cache

[1]  Sang-Won Lee,et al.  A log buffer-based flash translation layer using fully-associative sector translation , 2007, TECS.

[2]  Tei-Wei Kuo,et al.  An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[3]  Youngjoon Choi,et al.  A High Performance Controller for NAND Flash-based Solid State Disk (NSSD) , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

[4]  Tei-Wei Kuo,et al.  A space-efficient caching mechanism for flash-memory address translation , 2006, Ninth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'06).

[5]  Heeseung Jo,et al.  A superblock-based flash translation layer for NAND flash memory , 2006, EMSOFT '06.