Design and implementing method of multimedia expansion instructionof flow input read

This invention discloses a design and realization method for multimedia expansion instructions of reading stream input, in which, said method designs 4 media expansion instructions for the stream data input reading in an audio-video decoder, the hardware structure includes two 32 bit buffer-registers, an Adddr reading code streams, a Flag register, a Left register and two shifters to any bits, said expansion instruction includes Bini, Bread, Bload and a current Bpos, which also designs a hardware realization circuit of said stream data reading instruction and plot of pipelines in a processor to provide an instruction code mode in the SPARC V8 processor and experiment shows that the efficiency of said instruction is 5-8 times of the optimized artificial SPARC V8.