Impact of TSV Scaling on 3D IC Design Quality

TSVs incur two major kinds of overhead in the design of 3D ICs. First, TSVs lead to significant silicon area overhead. In addition, the non-negligible TSV parasitic capacitance causes delay overhead in 3D signal paths. Therefore, the possibility of obtaining all the benefits such as wirelength reduction and better performance from 3D ICs is highly dependent on TSV size and TSV capacitance. Meanwhile, TSVs are getting smaller to minimize their negative effects and sub-micron TSVs are expected to be fabricated in the near future. At the same time, the device size is also being downscaled beyond 32 and 22 nm, so it is highly likely that future 3D ICs are built with sub-micron TSVs and advanced device technologies. In this chapter, we study the impact of sub-micron TSVs on the quality of today and future 3D ICs. For future process technologies, we develop 22 and 16 nm libraries. Using these future process libraries as well as a 45 nm library, we generate 3D IC layouts with different TSV sizes and capacitances and study the impact of sub-micron TSVs thoroughly.

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