무선 전력 전송용 Low-dropout(LDO) Regulator 설계

In this paper, the proposed Low-dropout(LDO) regulator provides high stability and body biasing controlled circuit for improving a power supply rejection ratio(PSRR) of a LDO. The proposed LDO has been implemented in a commercial 0.35um CMOS technology, and the active chip area is 620um * 670um. The proposed LDO drivers a load current about 500㎃, dissipates 108uA quiescent current. The power supply rejection ratio(PSRR) at 1MHz is -42㏈.