Failure Mechanisms and Testing in Nanometer Technologies

[1]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production IDDQ testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[2]  Kwang-Ting Cheng,et al.  New challenges in delay testing of nanometer, multigigahertz designs , 2004, IEEE Design & Test of Computers.

[3]  Daniel C. Edelstein,et al.  On-chip wiring design challenges for gigahertz operation , 2001, Proc. IEEE.

[4]  Anthony C. Miller I/sub DDQ/ testing in deep submicron integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  Kaushik Roy,et al.  Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.

[6]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[7]  Madhav P. Desai,et al.  The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance , 2002 .

[8]  W. Abadeer,et al.  Behavior of NBTI under AC dynamic circuit conditions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[9]  R. Degraeve,et al.  Relation between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[10]  David Turner,et al.  Screening minVDD outliers using feed-forward voltage testing , 2002, Proceedings. International Test Conference.

[11]  Donald J. Grosch,et al.  Ballistics help determine the cause of the Columbia loss , 2004 .

[12]  Claude Thibeault An histogram based procedure for current testing of active defects , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  Ruiqi Tian,et al.  Reticle enhancement technology: implications and challenges for physical design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[15]  Melvin A. Breuer,et al.  Process variations and their impact on circuit operation , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[16]  Víctor H. Champac,et al.  Quiescent current analysis and experimentation of defective CMOS circuits , 1992, J. Electron. Test..

[17]  Jaume Segura,et al.  CMOS Electronics: How It Works, How It Fails , 2004 .

[18]  R. Keith Treece,et al.  CMOS IC stuck-open-fault electrical effects and design considerations , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[19]  Kwang-Ting Cheng,et al.  Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[21]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[22]  A. Keshavarzi,et al.  Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanism , 2004, 2004 International Conferce on Test.

[23]  J. Suehle Ultrathin Gate Oxide Breakdown: A Failure That We Can Live With? , 2004, EDFA Technical Articles.

[24]  Yuan Taur,et al.  CMOS design near the limit of scaling , 2002 .

[25]  Antonio Rubio,et al.  A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[26]  T. E. Turner A step-by-step method for elimination of burn-in as a necessary screen , 1996, 1996 International Integrated Reliability Workshop Final Report.

[27]  James McNames,et al.  Neighbor selection for variance reduction in I/sub DDQ/ and other parametric data , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[28]  A. Keshavarzi,et al.  A statistical model for extracting geometric sources of transistor performance variation , 2004, IEEE Transactions on Electron Devices.

[29]  D. Boning,et al.  Technology scaling impact of variation on clock skew and interconnect delay , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[30]  Wojciech Maly,et al.  Current signatures: application , 1997, Proceedings International Test Conference 1997.

[31]  Kaushik Roy,et al.  Multiple-parameter CMOS IC testing with increased sensitivity for I/sub DDQ/ , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[32]  Ali Keshavarzi,et al.  Parametric failures in CMOS ICs - a defect-based analysis , 2002, Proceedings. International Test Conference.