Exponentially Tapering Ground Wires for Elmore Delay Reduction in On Chip Interconnects

In this paper inter metal capacitors of ground wires are considered, for the first time in Elmore delay calculations of clock distribution interconnect networks. Analytical models for capacitance calculation of inter metal wires which are exponentially tapered are presented. In addition, the tapering of the ground wire for reducing this delay is proposed. The results show that by a exponentially tapering of the ground wires in the clock distribution networks , a 17% reduction in the Elmore delay of interconnects is achieved in compare with not tapering ground wires.

[1]  Alina Deutsch,et al.  Designing the best clock distribution network , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[2]  John Philip Fishburn,et al.  Shaping a distributed-rc line to minimize elmore delay , 1995 .

[3]  Jaijeet Roychowdhury.  Avoiding dispersion in distributed RLC lines by shaping , 1995, Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95).

[4]  Eby G. Friedman,et al.  Exponentially tapered H-tree clock distribution networks , 2005, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[5]  D. Cheng.  Field and wave electromagnetics , 1983 .

[6]  Fei Li,et al.  Vdd programmability to reduce FPGA interconnect power , 2004, ICCAD 2004.

[7]  Yehea I. Ismail,et al.  Figures of merit to characterize the importance of on-chip inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[8]  Charlie Chung-Ping Chen,et al.  Optimal wire-sizing function with fringing capacitance consideration , 1997, DAC.

[9]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.

[10]  L. Vandenberghe,et al.  Optimal wire and transistor sizing for circuits with non-tree topology , 1997, ICCAD 1997.

[11]  E.G. Friedman,et al.  Optimum wire shaping of an RLC interconnect , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[12]  Andrew B. Kahng,et al.  The Y architecture for on-chip interconnect: analysis and methodology , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Jamil Kawa,et al.  Managing on-chip inductive effects , 2002, IEEE Trans. Very Large Scale Integr. Syst..