SSTL IO standard based power efficient data processing device design on FPGA

In this paper, we have designed a power efficient data center using SSTL I/O standards. We have compared the performance of our data processing device through different processors. To increase the performance, Stub-Series Terminated Logic I/O standards are used. 17 distinct functions were performed on DPD that calculated the capability of four distinct processors. At operating frequency of 1.9 GHz of AMD x2150, a significant reduction of clock power, logic power and signal power is observed as 84.47%, 45% and 41.02% respectively. Minimization in DSP power, IO power is 44.4% & 18% respectively when we apply AMD x2150 at 1.9GHz in preference to Intel Xeon E7-8893, operating at 3.4 GHz. By doing the analysis, the best results are obtained while using AMD x2150 at 1.9GHz. This paper provides a novel FPGA based design for power efficient data processing device.

[1]  Bishwajeet Pandey,et al.  Design of frame buffer for 1 THz energy efficient digital image processor based on HSLVDCI I/O standard in FPGA , 2013, 2013 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION (ICSC).

[2]  Jang Ju-wook,et al.  Energy-Efficient Signal Processing Using FPGAs , 2005 .

[3]  Vanish Talwar,et al.  No "power" struggles: coordinated multi-level power management for the data center , 2008, ASPLOS.

[4]  B. Pandey,et al.  Simulation of voltage based efficient fire sensor on FPGA using SSTL IO standards , 2014, 2014 International Conference on Robotics and Emerging Allied Technologies in Engineering (iCREATE).

[5]  K. Chapman.  SEU Strategies for Virtex-5 Devices , 2010 .

[6]  RanganathanParthasarathy,et al.  No "power" struggles , 2008 .

[7]  Jean-Jacques Quisquater,et al.  Implementation of the AES-128 on Virtex-5 FPGAs , 2008, AFRICACRYPT.

[8]  Bishwajeet Pandey,et al.  IO Standard Based Green Multiplexer Design and Implementation on FPGA , 2013, 2013 5th International Conference on Computational Intelligence and Communication Networks.

[9]  Bishwajeet Pandey,et al.  SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA , 2014, 3rd International Symposium on Environmental Friendly Energies and Applications (EFEA).

[10]  Tanesh Kumar,et al.  SSTL based green image ALU design on different FPGA , 2013, 2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE).