An Input-Feedforward Multibit Adder-Less $\Delta{-}\Sigma$ Modulator for Ultrasound Imaging Systems

This paper describes a high-speed delta-sigma modulator with 65-nm CMOS technology for ultrasound imaging systems. The delta-sigma modulator is based on a 4th-order single-loop switched-capacitor architecture with a 4-bit quantizer. The designed modulator has the advantages associated with input-feedforward architecture, such as the reduced output swing of the integrator, which relaxes the amplifiers' design requirements. Due to the power and area overheads and the timing constraint of the active adder in the conventional multibit input-feedforward modulator, we use an adder-less input-feedforward delta-sigma architecture. As a result, the designed architecture eliminates the extra power consumption and silicon area required by the adder. The designed architecture also relaxes the timing requirement for the quantizer and the dynamic element-matching block compared with the conventional delta-sigma modulator. The modulator achieves a dynamic range of 76dB and a peak signal-to-noise-plus-distortion ratio of 72.3 dB in a signal bandwidth of 6 MHz. The power consumption is 18.5 mW with 1.2-V supply voltage, and the chip core size is 0.25 mm2. The energy required per conversion step is 0.46 pJ/conv.

[1]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[2]  Michiel Steyaert,et al.  Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS , 2006 .

[3]  Bernhard E. Boser,et al.  17.6 A Fourth-Order Σ∆ Interface for Micromachined Inertial Sensors , 2004 .

[4]  Zhimin Li,et al.  A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth , 2007, IEEE Journal of Solid-State Circuits.

[5]  P.R. Gray,et al.  A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR , 2004, IEEE Journal of Solid-State Circuits.

[6]  Karl-Erik Rydler,et al.  A Precision Current Source Using Delta- Sigma Modulation , 2011, IEEE Trans. Instrum. Meas..

[7]  Gabor C. Temes,et al.  A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. , 2012 .

[8]  B. Wooley,et al.  A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS , 1997, IEEE J. Solid State Circuits.

[9]  Gabor C. Temes,et al.  A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Yi-Gyeong Kim,et al.  A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppression Switches , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[12]  Michiel Steyaert,et al.  Design of Multi-Bit Delta-SIGMA A/D Converters , 2002 .

[13]  Domenico Luca Carnì,et al.  $SigmaDelta$ADC-Based Frequency-Error Measurement in Single-Carrier Digital Modulations , 2006, IEEE Transactions on Instrumentation and Measurement.

[14]  Boby George,et al.  Analysis of a Sigma–Delta Resistance-to-Digital Converter for Differential Resistive Sensors , 2009, IEEE Transactions on Instrumentation and Measurement.

[15]  José Manuel de la Rosa,et al.  Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  John G. Kauffman,et al.  An 8.5 mW Continuous-Time $\Delta \Sigma $ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR , 2011, IEEE Journal of Solid-State Circuits.

[17]  Jeongjin Roh,et al.  A Bufferless Interface for Single-Ended ECM Sensors , 2012, IEEE Transactions on Instrumentation and Measurement.

[18]  P. Malcovati,et al.  A fourth-order single-bit switched-capacitor /spl Sigma/-/spl Delta/ modulator for distributed sensor applications , 2004, IEEE Transactions on Instrumentation and Measurement.

[19]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[20]  W. Sansen,et al.  A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.

[21]  Koichi Hamashita,et al.  Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC , 2010, IEEE Journal of Solid-State Circuits.

[22]  Pengyu Song,et al.  A CMOS 3.4 mW 200 MHz continuous-time delta-sigma modulator with 61.5 dB dynamic range and 5 MHz bandwidth for ultrasound application , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[23]  B.E. Boser,et al.  A fourth-order /spl Sigma//spl Delta/ interface for micromachined inertial sensors , 2004, IEEE Journal of Solid-State Circuits.

[24]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[25]  George Jie Yuan,et al.  An Interpolation-Based Calibration Architecture for Pipeline ADC With Nonlinear Error , 2012, IEEE Transactions on Instrumentation and Measurement.

[26]  A.L. Coban,et al.  A 1.5 V 1.0 mW audio /spl Delta//spl Sigma/ modulator with 98 dB dynamic range , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[27]  Peter Händel,et al.  Postcorrection of Pipelined Analog–Digital Converters Based on Input-Dependent Integral Nonlinearity Modeling , 2011, IEEE Transactions on Instrumentation and Measurement.

[28]  Gerd Vandersteen,et al.  An ARMAX Identification Method for Sigma–Delta Modulators Using Only Input-Output Data , 2010, IEEE Transactions on Instrumentation and Measurement.

[29]  KiYoung Nam,et al.  A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion , 2005, IEEE Journal of Solid-State Circuits.

[30]  D.A. Johns,et al.  A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator , 2009, IEEE Journal of Solid-State Circuits.

[31]  Terri S. Fiez,et al.  Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging. , 1995 .

[32]  Luis Palafox,et al.  Design and Characterization of a Sampling System Based on $\Sigma$–$\Delta$ Analog-to-Digital Converters for Electrical Metrology , 2009, IEEE Transactions on Instrumentation and Measurement.

[33]  Yi-Gyeong Kim,et al.  A 0.9-V 60-$\mu{\hbox {W}}$ 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range , 2008, IEEE Journal of Solid-State Circuits.

[34]  Yoshihisa Fujimoto,et al.  A 100 MS/s 4 MHz Bandwidth 70 dB SNR $\Delta \Sigma$ ADC in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[35]  Gabor C. Temes,et al.  A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR , 2008, IEEE Journal of Solid-State Circuits.

[36]  Ahmed Gharbiya,et al.  On the implementation of input-feedforward delta-sigma modulators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[37]  B. A. Wooley,et al.  A 1.8-V digital-audio sigma-delta modulator in 0.8-/spl mu/m CMOS , 1997 .

[38]  Eby G. Friedman,et al.  A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applications , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[39]  Gabor C. Temes,et al.  An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD , 2009, IEEE J. Solid State Circuits.

[40]  Thomas Burger,et al.  A 0.13/spl mu/m CMOS EDGE/UMTS/WLAN Tri-Mode /spl Delta//spl Sigma/ ADC with -92dB THD , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[41]  Terri S. Fiez,et al.  Improved /spl Delta//spl Sigma/ DAC linearity using data weighted averaging , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[42]  B.K. Ahuja,et al.  An improved frequency compensation technique for CMOS operational amplifiers , 1983, IEEE Journal of Solid-State Circuits.