Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns

The ever-increasing test data volume for core-based system-on-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test access mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.

[1]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Yervant Zorian,et al.  Overview of the IEEE P1500 standard , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[3]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[4]  Krishnendu Chakrabarty,et al.  Test data compression for IP embedded cores using selective encoding of scan slices , 2005, IEEE International Conference on Test, 2005..

[5]  Bashir M. Al-Hashimi,et al.  A compression-driven test access mechanism design approach , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[6]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[7]  V. Iyengar,et al.  Unified SOC test approach based on test data compression and TAM design , 2005 .

[8]  Erik Jan Marinissen,et al.  Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip , 2003, IEEE Trans. Computers.

[9]  Kwame Osei Boateng,et al.  BIST-aided scan test - a new method for test cost reduction , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[10]  Erik Jan Marinissen,et al.  SOC test architecture design for efficient utilization of test bandwidth , 2003, TODE.

[11]  Brion L. Keller,et al.  A SmartBIST variant with guaranteed encoding , 2001, Proceedings 10th Asian Test Symposium.

[12]  Krishnendu Chakrabarty,et al.  SOC test planning using virtual test access architectures , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Qiang Xu,et al.  Multi-frequency test access mechanism design for modular SOC testing , 2004, 13th Asian Test Symposium.

[14]  Kohei Miyase,et al.  On identifying don't care inputs of test patterns for combinational circuits , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[15]  Vikram Iyengar,et al.  A unified SOC test approach based on test data compression and TAM design , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[16]  Krishnendu Chakrabarty,et al.  SoC Testing Using LFSR Reseeding, and Scan-Slice- Based TAM Optimization and Test Scheduling , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.