High-speed translation lookaside buffer

A translation lookaside buffer, which includes a plurality of virtual address comparing circuits, a plurality of word line drivers, and a plurality of storing circuits. The plurality of virtual address comparing circuits receive a virtual address, compare the virtual address with each of virtual address tags, and output a control signal in response to the compared result. The plurality of word line drivers receive the control signal output from the plurality of virtual address comparing circuits to activate a word line corresponding to the control signal. The plurality of storing circuits include first and second memory cells connected to the word line and output physical addresses stored in the first and second memory cells in response to the activation of the word line. Each of the plurality of storing circuits has a buffer between a node to which the first memory cells and the word line are connected and a node to which the second memory cells and the word line are connected. Accordingly, the speed of a translation lookaside buffer can operate at higher speed.