Applying a submicron mismatch model to practical IC design

A model of the mismatch effect in IC devices is presented that extends the validity of existing models to the sub-micron region. Unlike in previous studies the effect of a finite two dimensional correlation length is taken into account, thus allowing a good reproduction of the differences in device variance that occur for different aspect ratios. The model has been characterized on a 0.75 /spl mu/ CMOS technology and has been implemented in a powerful CAD system for statistical design analysis, thus being of practical utility for IC designers when making critical design considerations and trade-offs.<<ETX>>

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