Bipolar transistor modeling of avalanche generation for computer circuit simulation
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[1] J. L. Moll,et al. Multiplication in collector junctions of silicon n-p-n and p-n-p transistors , 1970 .
[2] S. L. Miller. Ionization Rates for Holes and Electrons in Silicon , 1957 .
[3] D. O. Pederson,et al. SLIC-a simulator for linear integrated circuits , 1971 .
[4] P. L. Hower,et al. Avalanche injection and second breakdown in transistors , 1970 .
[5] W. J. McCalla,et al. BIAS-3-A program for the nonlinear D.C. analysis of bipolar transistor circuits , 1970 .
[6] R. A. Kokosa,et al. Avalanche breakdown of diffused silicon p-n junctions , 1966 .
[7] H. C. Poon,et al. Modeling of avalanche effect in integral charge control model , 1972 .
[8] J. G. Fossum. A bipolar device modeling technique applicable to computer-aided circuit analysis and design , 1973 .
[9] C. Bulucea,et al. The calculation of the avalanche multiplication factor in silicon p—N junctions taking into account the carrier generation (thermal or optical) in the space-charge region , 1973 .