A universal self-calibrating Dynamic Voltage and Frequency Scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs

Field Programmable Gate Arrays (FPGAs) are widely used in telecom, medical, military and cloud computing applications. Unlike in microprocessors, the routing and critical path delay of FPGAs is user dependent. The design tool suggests a maximum operating frequency based on the worst-case timing analysis of the critical paths at a fixed nominal voltage, which usually means there is significant voltage or frequency margin in a typical chip. This paper presents a universal offline self-calibration scheme, which automatically finds the FPGA frequency and core voltage operating limit at different self-imposed temperatures by monitoring design-specific critical paths. These operating points are stored in a calibration table and used to dynamically adjust the frequency and core voltage according to the FPGA temperature when the application circuit is running. The self-calibration process is demonstrated on an Altera Cyclone IV 65-nm FPGA with a digitally controlled dc-dc converter, leading to 40% power savings in a typical digital filter application.

[1]  O. Trescases,et al.  DC–DC Converter With Digital Adaptive Slope Control in Auxiliary Phase for Optimal Transient Response and Improved Efficiency , 2012, IEEE Transactions on Power Electronics.

[2]  Stephen P. Boyd,et al.  Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  John Sartori,et al.  Enhancing the Efficiency of Energy-Constrained DVFS Designs , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Kwen-Siong Chong,et al.  An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive $V_{\rm DD}$ System for Wireless Sensor Networks , 2013, IEEE Journal of Solid-State Circuits.

[5]  Peter Y. K. Cheung,et al.  Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling , 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

[6]  Bharat Sukhwani,et al.  Database Analytics: A Reconfigurable-Computing Approach , 2014, IEEE Micro.

[7]  Wayne Luk,et al.  Dynamic voltage scaling for commercial FPGAs , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[8]  James R. Larus,et al.  A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services , 2015, IEEE Micro.

[9]  Jiann-Liang Chen,et al.  A Power Saving Mechanism for Multimedia Streaming Services in Cloud Computing , 2014, IEEE Systems Journal.

[10]  Hidetoshi Onodera,et al.  Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Peter Y. K. Cheung,et al.  Dynamic voltage & frequency scaling with online slack measurement , 2014, FPGA.

[12]  Wai Tung Ng,et al.  Variable output, soft-switching DC/DC converter for VLSI dynamic voltage scaling power supply applications , 2004, 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551).

[13]  Jan Kuper,et al.  On the Interplay between Global DVFS and Scheduling Tasks with Precedence Constraints , 2015, IEEE Transactions on Computers.

[14]  Mario R. Casu,et al.  LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  Hari Angepat,et al.  An FPGA-based In-Line Accelerator for Memcached , 2014, IEEE Computer Architecture Letters.

[16]  Peter Y. K. Cheung,et al.  SMI: Slack Measurement Insertion for online timing monitoring in FPGAs , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[17]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  M.R.D. Al-Mothafar,et al.  Small-signal modelling of peak current-mode controlled buck-derived circuits , 1999 .

[19]  Na Gong,et al.  TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.