Test enrichment for path delay faults using multiple sets of target faults

Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures since shorter paths may fail without any of the longest paths failing. In addition, paths that appear to be shorter may actually be longer than the longest paths if the procedure used for estimating path length is inaccurate. We propose a test enrichment procedure that increases significantly the number of faults associated with the next-to-longest paths that are detected by a (compact) test set. This is achieved by allowing the underlying test generation procedure the flexibility of detecting or not detecting the faults associated with the next-to-longest paths. Faults associated with next.-to-longest paths are detected without increasing the number of tests beyond that required to detect the faults associated with the longest paths. The proposed procedure thus improves the quality of the test set without increasing its size.

[1]  Sudhakar M. Reddy,et al.  Fast Identification of Robust Dependent Path Delay Faults , 1995, 32nd Design Automation Conference.

[2]  Irith Pomeranz,et al.  An efficient non-enumerative method to estimate path delay fault coverage , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[3]  Dhiraj K. Pradhan,et al.  A method to derive compact test sets for path delay faults in combinational circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[4]  M. Lakshmi Narasimha Reddy Compact test sets for digital logic circuits , 1992 .

[5]  Kwang-Ting Cheng,et al.  Delay testing for non-robust untestable circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[6]  Soumitra Bose,et al.  Generation of compact delay tests by multiple path activation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[7]  S. Sahni,et al.  On path selection in combinational logic circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[8]  Irith Pomeranz,et al.  On Synthesis-for-Testability of Combinational Logic Circuits , 1995, 32nd Design Automation Conference.

[9]  Michael H. Schulz,et al.  DYNAMITE: an efficient automatic test pattern generation system for path delay faults , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Irith Pomeranz,et al.  A method for identifying robust dependent and functionally unsensitizable paths , 1997, Proceedings Tenth International Conference on VLSI Design.

[11]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[12]  Michael H. Schulz,et al.  Advanced automatic test pattern generation techniques for path delay faults , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.