A cell set for self-timed design using actel FPGAs

Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. However, these systems require that suitable self-timed circuit primitives are available for building the system. This report describes a cell set designed for building self-timed circuits and systems using Actel field programmable gate arrays (FPGAs). The cells use a two-phase transition signalling protocol for control signals and a bundled protocol for data signals. This library of macro cells is designed to be used with the Work view tool suite from VIEW logic and the Action Logic System (ALS) from Actel. As VLSI technology improves, the systems that can be built become larger, faster, and more complex. Along with these improvements, however, come many problems directly associated with the speed and scale o f the new systems. In particular, timing problems become severe and account for more and more o f the design and debugging expense. A major culprit is the traditional synchronous design style in which all the system components are synchronized to a global clock. One solution is to use asynchronous or self-timed [13] techniques. Self-timed circuits avoid clock-related timing problems by enforcing a simple communication protocol which is insensitive to delays in circuit components or the wires that arc used to connect them. The design o f asynchronous or self-timed circuits and systems has long been con­ sidered too difficult by all but a few researchers and engineers. One reason for this perception is that a long history o f designing synchronous circuits has resulted in a great deal o f knowledge and large variety o f tools to aid in that style o f circuit design. The same level o f support for asynchronous design does not exist at present. Because there is no great demand for these circuits, semiconductor manufacturers do not offer commercially available parts that are suitable for asynchronous design. This only reinforces the tendency to design traditional synchronous systems. Asynchronous design is, however, currently attracting renewed interest as a method for coping with some o f the problems associated with improved VLSI technology. The