On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements

Current printability issues can be attributed to sub-wavelength lithography and its sensitivity to manufacturing process variations. Resulting process variations cause performance, yield and reliability problems. As noted in ITRS, conventional burn-in test is losing cost-effectiveness in reliability screening. In this paper, we use lithography process corner information in reliability screening. The lithographic process corner information is decoded from circuit measurements using a tester. We propose two methodologies for binning of dies based on Mean Time to Failure (MTTF). Lithography aware LUT based binning uses pre-estimated MTTF values to bin dies based on the detected litho-process corner. Lithography aware pattern based binning uses test patterns specific to litho-process corner along with existing techniques like burn-in test or Electrical Line width Metrology (ELM). Accurate determination of die level process corner is an important step employed in the proposed methodology. This work aims at: a) test Pattern generation for increased reliability test coverage incorporating manufacturing variations, b) utilization of die based process corner information for choosing the best test pattern set for improved fault coverage, c) achieving acceleration of infant mortality within the manufacturing test flow, and d) die-level determination of MTTF incorporating lithography process variation and hence decreasing the binning-yield loss. Experiments on ISCAS'85 circuits for varying exposure dose and de-focus values show an average variation of 20-30nm in interconnect widths, resulting in a deviation of as much as 40% in the estimated MTTF. It is also observed that, for maximum fault coverage, the test vector set changes in size and pattern across various process corners.

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