Impact of Off State Stress on advanced high-K metal gate NMOSFETs

In this work we have investigated the impact of Off State Stress (OSS) on nMOSFETs in High-K/Metal Gate (HKMG) technology. Although in standard poly-SiO2/SiON devices the impact of OSS is relatively limited and causes an increase in VTH, in the case of HKMG larger degradation is observed, with negative VTH shift. A significant increase of the device Off state leakage is observed, causing a serious issue for high voltage and low power oriented circuits.

[1]  M.A. Alam,et al.  Universality of Off-State Degradation in Drain Extended NMOS Transistors , 2006, 2006 International Electron Devices Meeting.

[2]  R. Degraeve,et al.  Ion-implantation-based low-cost Hk/MG process for CMOS low-power application , 2010, 2010 Symposium on VLSI Technology.

[3]  Roles of electron trapping and interface state generation on gate-induced drain leakage current in p-MOSFETs , 1991, IEEE Electron Device Letters.

[4]  S.-J. Choi,et al.  A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[5]  K. Hofmann,et al.  A comprehensive analysis of NFET degradation due to off-state stress , 2004, IEEE International Integrated Reliability Workshop Final Report, 2004.

[6]  Naoto Horiguchi,et al.  Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs , 2013, IEEE Transactions on Electron Devices.

[7]  L. Pantisano,et al.  Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics , 2003, IEEE Electron Device Letters.

[8]  Chenming Hu,et al.  A thermal activation view of low voltage impact ionization in MOSFETs , 2002, IEEE Electron Device Letters.

[9]  Srikanth Krishnan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2005, Microelectron. Reliab..

[10]  Martin M. Frank.  High-k / metal gate innovations enabling continued CMOS scaling , 2011 .

[11]  V. Huard,et al.  Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature , 2009, 2009 IEEE International Reliability Physics Symposium.

[12]  B. Kang,et al.  Effect of off-State Stress and Drain Relaxation Voltage on Degradation of a Nanoscale nMOSFET at High Temperature , 2011, IEEE Electron Device Letters.

[13]  S. Natarajan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[14]  C. Hu,et al.  A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation , 1991 .

[15]  A. Muehlhoff.  An Extrapolation Model for Lifetime Prediction for Off-State - Degradation of MOS-FETs , 2001, Microelectron. Reliab..