Customized Core Layout: A Case Study on Dual-Core Dynamic Binary Translation System

High efficient hardware accelerators are customized to improve the performance of applications from special domains. In this paper, we try to answer the question of where should we integrate a customized processor core to accelerate an application via comparing the performance on different multi-core platforms. We select dynamic binary translation as example application. First, we establish a performance model for software DBT system and describe its design space. Then, we build an abstract architecture of dual-core DBT system, and list three possible locations to integrate a customized accelerator. Finally, we did simulation on the three platforms with the customized DBT core integrated in the different locations, and discussed the result. By the result of the simulation, we have proved that the DBT can be speedup by the dual-core platform, and the platform 2 with a customized core on DIMM shows the best performance (about 48% compared with the single core DBT).

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