A Holistic Approach Towards Intelligent Hotspot Prevention in Network-on-Chip-Based Multicores
暂无分享,去创建一个
Theocharis Theocharides | Elena Kakoulli | Vassos Soteriou | T. Theocharides | V. Soteriou | E. Kakoulli
[1] DaeHo Seo,et al. Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks , 2005, ISCA 2005.
[2] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[3] Natalie D. Enright Jerger,et al. DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[4] Mithuna Thottethodi,et al. Self-tuned congestion control for multiprocessor networks , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.
[5] Fernando Gehm Moraes,et al. Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip , 2010, SBCCI '10.
[6] Radu Marculescu,et al. DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..
[7] Theocharis Theocharides,et al. Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Aaron Smith,et al. Compiling for EDGE architectures , 2006, International Symposium on Code Generation and Optimization (CGO'06).
[9] Radu Marculescu,et al. A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture , 2012, CODES+ISSS.
[10] Stephen W. Keckler,et al. Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[11] Theocharis Theocharides,et al. HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).
[12] Hamid Sarbazi-Azad,et al. Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic , 2001, IEEE Trans. Computers.
[13] Masoud Daneshtalab,et al. BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs , 2008, 2008 Design, Automation and Test in Europe.
[14] Pedro López,et al. A family of mechanisms for congestion control in wormhole networks , 2005, IEEE Transactions on Parallel and Distributed Systems.
[15] Scott H. Cameron. PIECE-WISE LINEAR APPROXIMATIONS , 1966 .
[16] Akif Ali,et al. Near-optimal worst-case throughput routing for two-dimensional mesh networks , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[17] Axel Jantsch,et al. Load distribution with the proximity congestion awareness in a network on chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[18] Saurabh Dighe,et al. A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.
[19] José Duato,et al. A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks , 1993, IEEE Trans. Parallel Distributed Syst..
[20] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[21] Derek L. Eager,et al. A Novel Strategy for Controlling Hot Spot Congestion , 1989, ICPP.
[22] Radu Marculescu,et al. Quantum-Like Effects in Network-on-Chip Buffers Behavior , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[23] Natalie D. Enright Jerger,et al. Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[24] Narayanan Vijaykrishnan,et al. Evaluating alternative implementations for LDPC decoder check node function , 2004, IEEE Computer Society Annual Symposium on VLSI.
[25] Masoud Daneshtalab,et al. NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).
[26] Doug Burger,et al. Implementation and Evaluation of On-Chip Network Architectures , 2006, 2006 International Conference on Computer Design.
[27] Ming Li,et al. DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[28] Alexander Sprintson,et al. GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip , 2016, IEEE Trans. Parallel Distributed Syst..
[29] Bill Lin,et al. Destination-based adaptive routing on 2D mesh networks , 2010, 2010 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).
[30] Ran Ginosar,et al. Access Regulation to Hot-Modules in Wormhole NoCs , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[31] Simha Sethumadhavan,et al. Distributed Microarchitectural Protocols in the TRIPS Prototype Processor , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[32] William J. Dally,et al. A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.
[33] Anil K. Jain,et al. Artificial Neural Networks: A Tutorial , 1996, Computer.