The AlphaServer 8000 Series: High-end Server Platform Development

The AlphaServer 8400 and the AlphaServer 8200 are Digital's newest high-end server products. Both servers are based on the 300-MHz Alpha 21164 microprocessor and on the AlphaServer 8000-series platform architecture. The AlphaServer 8000 platform development team set aggressive system data bandwidth and memory read latency targets in order to achieve high-performance goals. The low-latency criterion was factored into design decisions made at each of the seven layers of platform development. The combination of industry-leading microprocessor technology and a system platform focused on low latency has resulted in a 12-processor server implementation--the AlphaServer 8400--capable of supercomputer levels of performance.

[1]  Jack J. Dongarra,et al.  Performance of various computers using standard linear equations software in a FORTRAN environment , 1988, CARN.

[2]  Richard B. Watson,et al.  Clock Buffer Chip With Absolute Delay Regulation Over Process And Environmental Variations , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[3]  Jean H. Basmaji,et al.  Digital's High-performance CMOS ASIC , 1995, Digit. Tech. J..

[4]  Subhash Saini,et al.  NAS Parallel Benchmarks Results 3-95 , 1995 .

[5]  E. Davidson.  Delay factors for mainframe computers , 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.

[6]  William J. Bowhill,et al.  Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU , 1995, Digit. Tech. J..

[7]  Zarka Cvetanovic,et al.  Characterization of Alpha AXP performance using TP and SPEC workloads , 1994, Proceedings of 21 International Symposium on Computer Architecture.

[8]  Loren Staley.  A new MP HW architecture for technical and commercial environments , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.

[9]  Douglas W. Stout,et al.  VLSI performance compensation for off-chip drivers and clock generation , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[10]  D. Le,et al.  A dynamically tracking clock distribution chip with skew control , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[11]  M. G. Johnson,et al.  A Variable Delay Line Phase Locked Loop For Cpu-coprocessor Synchronization , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[12]  Catharine van Ingen,et al.  Technical Description of the DEC 7000 and DEC 10000 AXP Family , 1992, Digit. Tech. J..