High level abstraction of memristor model for neural network simulation

Memristor emerged as an auspicious device in the field of neuromorphic engineering due to its nanoscale size, non-volatility, scalability, fast switching, low power consumption, high density and compatability with CMOS technology. This paper unveils the first mathematical memristor modeling in C ++. We also represent the implementation and training of a single layer and multilayer neural network using C++ memristor model. The memristive crossbar structure has been utilized to train the network. We successfully demonstrated linear and non-linear seperable logic functions using C++ memristor modeling in the simulation of neural network. We also demonstrated pattern classifier using single layer neural network at two different learning rates and the network performs satisfactorily at both the learning rates.

[1]  Dalibor Biolek,et al.  SPICE Model of Memristor with Nonlinear Dopant Drift , 2009 .

[2]  Jennifer Hasler,et al.  Finding a roadmap to achieve large neuromorphic hardware systems , 2013, Front. Neurosci..

[3]  Massimiliano Di Ventra,et al.  Experimental demonstration of associative memory with memristive neural networks , 2009, Neural Networks.

[4]  Mark Horowitz,et al.  1.1 Computing's energy problem (and what we can do about it) , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[5]  Chris Yakopcic,et al.  Energy efficient perceptron pattern recognition using segmented memristor crossbar arrays , 2013, The 2013 International Joint Conference on Neural Networks (IJCNN).

[6]  S. Kvatinsky,et al.  Models of memristors for SPICE simulations , 2012, 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel.

[7]  Giacomo Indiveri,et al.  Frontiers in Neuromorphic Engineering , 2011, Front. Neurosci..

[8]  Jimson Mathew,et al.  High-performance single-cycle memristive multifunction logic architecture , 2016 .

[9]  Wei Yang Lu,et al.  Nanoscale memristor device as synapse in neuromorphic systems. , 2010, Nano letters.

[10]  Byoung Hun Lee,et al.  Neuromorphic Hardware System for Visual Pattern Recognition With Memristor Array and CMOS Neuron , 2015, IEEE Transactions on Industrial Electronics.

[11]  L. Chua Memristor-The missing circuit element , 1971 .

[12]  Karel Zaplatilek,et al.  Memristor modeling in MATLAB® &Simulink® , 2011 .

[13]  Ahmad Ayatollahi,et al.  STDP implementation using memristive nanodevice in CMOS-Nano neuromorphic networks , 2009, IEICE Electron. Express.

[14]  Peng Li,et al.  Nonvolatile memristor memory: Device characteristics and design implications , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[15]  M. R. McLean Concurrent Learning Algorithm and the Importance Map , 2014, Network Science and Cybersecurity.

[16]  Gregory S. Snider,et al.  Spike-timing-dependent learning in memristive nanodevices , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[17]  Garrett S. Rose,et al.  Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions , 2013, IEEE Transactions on Computers.

[18]  Junjie Wu,et al.  Image segmentation with threshold based on memristors , 2013, 2013 IEEE 4th International Conference on Electronics Information and Emergency Communication.

[19]  B. Mohammad,et al.  Mathematical modeling of a memristor device , 2012, 2012 International Conference on Innovations in Information Technology (IIT).

[20]  Massimiliano Di Ventra,et al.  Practical Approach to Programmable Analog Circuits With Memristors , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.