Optimal clock period FPGA technology mapping for sequential circuits
暂无分享,去创建一个
C.L. Liu | Peichen Pan | P. Pan | C. Liu
[1] Robert K. Brayton,et al. Sequential Synthesis for Table Look Up Programmable Gate Arrays , 1993, 30th ACM/IEEE Design Automation Conference.
[2] Donald E. Thomas,et al. Area and delay mapping for table-look-up based field programmable gate arrays , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[3] Nam Sung Woo. A heuristic method for FPGA technology mapping based on the edge visibility , 1991, 28th ACM/IEEE Design Automation Conference.
[4] Kevin Karplus. Xmap: a technology mapper for table-lookup field-programmable gate arrays , 1991, 28th ACM/IEEE Design Automation Conference.
[5] Martin D. F. Wong,et al. Edge-map: Optimal Performance Driven Technology Mapping for Iterative Lut Based Fpga Designs , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[6] Dwight D. Hill,et al. Routable technology mapping for LUT FPGAs , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.