A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators
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Luca Selmi | Pierpaolo Palestri | David Esseni | Roberto Nonis | Michele Nocente | Donald Fontanelli
[1] M. Horowitz,et al. Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2] Lizhong Sun,et al. A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator , 2001, IEEE J. Solid State Circuits.
[3] Ruiyuan Zhang,et al. Fast acquisition clock and data recovery circuit with low jitter , 2006, IEEE J. Solid State Circuits.
[4] Beomsup Kim,et al. A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS , 1999 .
[5] M. Sachdev,et al. An analytical equation for the oscillation frequency of high-frequency ring oscillators , 2004, IEEE Journal of Solid-State Circuits.
[6] Ramesh Harjani,et al. Design of low-phase-noise CMOS ring oscillators , 2002 .
[7] G. Knoblinger,et al. A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
[8] Manoj Sachdev,et al. A method to derive an equation for the oscillation frequency of a ring oscillator , 2003 .
[9] Y. A. Eken,et al. A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.
[10] Bosco H. Leung,et al. A novel model on phase noise of ring oscillator based on last passage time , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] C.A.T. Salama,et al. Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications , 2000, IEEE Journal of Solid-State Circuits.
[12] A.A. Abidi,et al. Phase Noise and Jitter in CMOS Ring Oscillators , 2006, IEEE Journal of Solid-State Circuits.
[13] Oscal T.-C. Chen,et al. A power-efficient wide-range phase-locked loop , 2002, IEEE J. Solid State Circuits.
[14] J.G. Maneatis,et al. Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[15] A. Hajimiri,et al. Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.
[16] Massimo Alioto,et al. Oscillation frequency in CML and ESCL ring oscillators , 2001 .
[17] Michael H. Perrott,et al. A numerical design approach for high speed, differential, resistor-loaded, CMOS amplifiers , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[18] Ali Hajimiri,et al. A general theory of phase noise in electrical oscillators , 1998 .
[19] T. Toifl,et al. 0.94ps-rms-jitter 0.016mm/sup 2/ 2.5GHz multi-phase generator PLL with 360/spl deg/ digitally programmable phase shift for 10Gb/s serial links , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[20] K. Tomioka,et al. A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC , 2006, IEEE Journal of Solid-State Circuits.
[21] Zhinian Shu,et al. A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture , 2004, IEEE Journal of Solid-State Circuits.
[22] Howard C. Luong,et al. A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers , 2001 .
[23] Deog-Kyoon Jeong,et al. A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique , 2005, IEEE Journal of Solid-State Circuits.