A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects

CMOS technology scaling has made the increase of transistor density in Systems-on-Chip (SoC) possible. In addition, the necessity of storing more and more information has resulted in the fact that Static Random Access Memories (SRAMs) have become great part of the SoC's silicon area. This miniaturization brings up several benefits, among them an increase of system performance. However, some undesirable behaviors, that did not exist or that were negligible, now became reality. Manufacturing process variation has introduced new types of defects, such as: (1) Resistive-Open defects and (2) Resistive-Bridge defects, which depending on their size can cause static or dynamic faults. Indeed, the circuit's sensibility to environmental noise is another challenge related to technology scaling. In more detail, the interference can damage the circuit behavior and cause Single Event Upsets (SEUs), affecting the circuit's reliability. Given these circumstances, this work proposes a hardware-based methodology able to detect resistive defects as well as to monitor defective cells in field aiming to detect SEUs. The fundamental idea is to use part of the hardware introduced to perform the manufacturing test to also detect bit-flips during the circuit's lifetime. Note that only SRAM cells with weak resistive defects are monitored, since the cells with strong defects that propagate static faults are isolated after manufacturing test. The proposed work has been validated and evaluated through SPICE simulations adopting an SRAM array modeled with a commercial 65nm CMOS technology library.