Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results

The purpose of this paper is to present experimental results validating a diagnosis method based on differential Iddq probabilistic signatures and on maximum likelihood estimation. First, SEMATECH Project S121 data is used to support assumptions about current behaviour. Then results obtained from an IC monitor containing controllable faults clearly show the capability of the method to identify the type of actual activated faults, in spite of a strong experimental current standard variation. These results validate previous simulation procedures, which are applied to estimate what can be expected with more common current standard variations.

[1]  C.F. Hawkins,et al.  Identifying defects in deep-submicron CMOS ICs , 1996, IEEE Spectrum.

[2]  Joan Figueras,et al.  On estimating bounds of the quiescent current for I/sub DDQ/ testing , 1996, Proceedings of 14th VLSI Test Symposium.

[3]  Richard E. Anderson,et al.  IC failure analysis: techniques and tools for quality and reliability improvement , 1995 .

[4]  Mark Storey,et al.  Microprocessor IDDQ Testing: A Case Study , 1995, IEEE Des. Test Comput..

[5]  Weitong Chuang,et al.  Circuit-level dictionaries of CMOS bridging faults , 1994, Proceedings of IEEE VLSI Test Symposium.

[6]  David L. Landis,et al.  A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs , 1996, Proceedings of 14th VLSI Test Symposium.

[7]  J. Figueras,et al.  I/sub DDQ/ test and diagnosis of CMOS circuits , 1995 .

[8]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[9]  P. Nigh,et al.  An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[10]  John G. Proakis,et al.  Digital Communications , 1983 .

[11]  Wojciech Maly,et al.  Statistical approach to VLSI , 1994 .

[12]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[13]  J. Soden,et al.  IC failure analysis: techniques and tools for quality reliability improvement , 1993, Proc. IEEE.

[14]  Joan Figueras,et al.  IDDQ Test and Diagnosis of CMOS Circuits , 1995, IEEE Design & Test of Computers.

[15]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[16]  Sreejit Chakravarty,et al.  Algorithms for IDDQ measurement based diagnosis of bridging faults , 1992, J. Electron. Test..

[17]  Wojciech Maly,et al.  Current signatures: application , 1997, Proceedings International Test Conference 1997.

[18]  Robert C. Aitken,et al.  Fault Location with Current Monitoring , 1991, 1991, Proceedings. International Test Conference.

[19]  Sheldon M. Ross Introduction to Probability Models. , 1995 .

[20]  Robert C. Aitken,et al.  Diagnosis of leakage faults with IDDQ , 1992, J. Electron. Test..

[21]  Claude Thibeault,et al.  Can the current behavior of faulty and fault-free ICs and the impact on diagnosis , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[22]  Wojciech Maly,et al.  Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.

[23]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[24]  Claude Thibeault,et al.  A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).