Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff

In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a maze router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly. We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.

[1]  Nils J. Nilsson,et al.  A Formal Basis for the Heuristic Determination of Minimum Cost Paths , 1968, IEEE Trans. Syst. Sci. Cybern..

[2]  Frank K. Hwang,et al.  The rectilinear steiner arborescence problem , 2005, Algorithmica.

[3]  Sung-Woo Hur,et al.  Timing driven maze routing , 1999, ISPD '99.

[4]  Igor L. Markov,et al.  Quadratic placement revisited , 1997, DAC.

[5]  Yici Cai,et al.  An efficient hierarchical timing-driven Steiner tree algorithm for global routing , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[6]  Marcelo de Oliveira Johann,et al.  Maze routing steiner trees with effective critical sink optimization , 2007, ISPD '07.

[7]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[8]  R. Reis,et al.  Net by net routing with a new path search algorithm , 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).

[9]  Xianlong Hong,et al.  Performance-Driven Steiner Tree Algorithms for Global Routing , 1993, 30th ACM/IEEE Design Automation Conference.

[10]  David R. Karger,et al.  Prim-Dijkstra tradeoffs for improved performance-driven routing tree design , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Somchai Prasitjutrakul,et al.  A timing-driven global router for custom chip design , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[12]  Jason Cong,et al.  Provably good performance-driven global routing , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Sachin S. Sapatnekar,et al.  Non-Hanan routing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  J. Donoghue Labyrinth , 1998, The Lancet.

[15]  Sung-Woo Hur,et al.  Timing-driven maze routing , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Jason Cong,et al.  Performance-Driven Interconnect Design Based on Distributed RC Delay Model , 1993, 30th ACM/IEEE Design Automation Conference.

[17]  M. Hanan,et al.  On Steiner’s Problem with Rectilinear Distance , 1966 .

[18]  C. Y. Lee An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[19]  Andrew B. Kahng,et al.  Near-optimal critical sink routing tree constructions , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Shantanu Dutt,et al.  Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[21]  Chung-Kuan Cheng,et al.  New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing , 1996, DAC '96.

[22]  Andrew B. Kahng,et al.  Timing-driven Steiner trees are (practically) free , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[23]  Martin Zachariasen,et al.  Rectilinear full Steiner tree generation , 1999, Networks.

[24]  Jason Cong,et al.  Interconnect layout optimization under higher order RLC model forMCM designs , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Mary Jane Irwin,et al.  A fast algorithm for minimizing the Elmore delay to identified critical sinks , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..