A Novel FPGA-Based Digital Power Controller Architecture

In this paper, we design a novel controller based on modular bus software and hardware architecture. The proposed controller uses the FPGA as the hardware carrier, and integrates the external expansion type Avalon bus with the discrete IP module structure to realize the all-digital, efficient and reliable fast closed-loop regulation power control. Based on the requirements of the original related functions, the digital controller greatly reduces the FPGA resource consumption and improves the efficiency of hardware resources. Meanwhile, it provides a powerful experimental data reference for the modular design of the digital power controller. Moreover, the designed controller is successfully applied on Cooler Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) six-pole magnet power supply.

[1]  Wei Zhang,et al.  The heavy ion cooler-storage-ring project (HIRFL-CSR) at Lanzhou , 2002 .

[2]  Pong P. Chu,et al.  Embedded SoPC Design with Nios II Processor and Verilog Examples: Chu/Embedded , 2011 .

[3]  R. D. Daruwala,et al.  Design and Implementation of Soft core Processor on FPGA based on Avalon Bus and SOPC Technology , 2013 .

[4]  Feng Lin,et al.  HW/SW interface synthesis based on Avalon bus specification for Nios-oriented SoC design , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[5]  Jing Chen,et al.  Design and construction of a time-of-flight wall detector at External Target Facility of HIRFL-CSR , 2018, Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment.

[6]  Pong P. Chu,et al.  Embedded SoPC Design with Nios II Processor and VHDL Examples , 2011 .

[7]  Zhenhua Wei,et al.  FIR Filter Design Based on FPGA , 2018, 2018 10th International Conference on Measuring Technology and Mechatronics Automation (ICMTMA).