Scan Architecture d resettable flip-flops and anti-SEU single event transient

The present invention discloses an anti-SEU single event transients and resets the D flip-scan structure, aimed at resolving the resettable D flip-flop of the scan configuration capabilities and anti-SEU single event transient is not high. The present invention consists of a buffer circuit, a scan control buffer circuit, a buffer circuit is reset, a clock circuit, a master latch, the latch and the composition from the output buffer circuit. Master latch and the slave latch reinforcement redundant latch. Master latch and the slave latch in series, and each clock circuit and reset buffer circuit. Also with the master latch buffer circuit, the scan control circuit connected to the buffer, the buffer is also connected to the output from the latch circuit. Separating the master latch and the slave latch circuit mutually redundant C2MOS improved resistance to SEU. Buffer circuit such that the longer the duration of a single event transient error does not occur under the dual-mode redundancy path to further increase the resistance to single event transient.