A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA

When conventional biasing topologies are employed, near sub-threshold operated amplifiers show large performance deviations under unavoidable PVT variations. Moreover, these effects become severe when these circuits are implemented in sub-nanometer technologies. This paper introduces a new type of compensation technique to realize a reliable low voltage, low-noise amplifier that is achieved by stabilizing the core device trans-conductance (gm). To minimize the gm variation, the proposed technique uses an error voltage generated by comparing the LNA current with a stable constant current reference (CCR). Not only the compensation circuits, a new low-voltage self-biased CCR source is also introduced which is based on conventional β multiplier that can operate with a voltage as low as 0.4 V with a resulting TC (temperature coefficient) of 118 ppm/°C for typical-typical corner case. The gm and S21 of the compensated 65 nm LNA core device shows 8 × times lower variations compared to that of a conventional one when temperature varies from -20 to +110°C and with the consideration of five process corner cases. Finally, Monte Carlo estimation for both process and mismatch shows 34% reduction in standard deviation of S21 and 20% improvement in yield compared to a conventionally biased LNA. The compensated LNA with all its accessories consumes only 402 μW power when operated at a supply voltage of 0.6 V.

[1]  Santiago Celma,et al.  Precision CMOS current reference with process and temperature compensation , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[2]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[3]  Abdelhalim Bendali,et al.  A 1-V CMOS Current Reference With Temperature and Process Compensation , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Abhijit Chatterjee,et al.  Design of process variation tolerant radio frequency low noise amplifier , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[5]  Harald Pretl,et al.  A circuit technique to compensate PVT variations in a 28 nm CMOS cascode power amplifier , 2015, 2015 German Microwave Conference.

[6]  Pavan Kumar Hanumolu,et al.  Constant transconductance bias circuit with an on-chip resistor , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[7]  Sunay Shah,et al.  A temperature independent trimmable current source , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[8]  Giuseppe Iannaccone,et al.  A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference , 2011, IEEE Journal of Solid-State Circuits.

[9]  Sameer R. Sonkusale,et al.  A PVT independent subthreshold constant-Gm stage for very low frequency applications , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[10]  Mustansir Yunus Mukadam,et al.  Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Jiann-Shiun Yuan,et al.  Adaptive Gate Bias for Power Amplifier Temperature Compensation , 2011, IEEE Transactions on Device and Materials Reliability.

[12]  Paolo Stefano Crovetti,et al.  A new compact temperature-compensated CMOS current reference , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[13]  Wei-Bin Yang,et al.  Temperature insensitive current reference for the 6.27 MHz oscillator , 2011, 2011 International Symposium on Integrated Circuits.

[14]  Randall L. Geiger,et al.  A CMOS supply-insensitive with 13ppm/°C temperature coefficient current reference , 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

[15]  Shanthi Pavan,et al.  Widely Programmable High-Frequency Active RC Filters in CMOS Technology , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[17]  G. Palumbo,et al.  A low-voltage low-power voltage reference based on subthreshold MOSFETs , 2003, IEEE J. Solid State Circuits.

[18]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[19]  Lih-Yih Chiou,et al.  An ultra-low-power adaptive-body-bias control for subthreshold circuits , 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

[20]  Jeongjin Roh,et al.  A 1.2-V 4.2- $\hbox{ppm}/^{\circ}\hbox{C}$ High-Order Curvature-Compensated CMOS Bandgap Reference , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Sunay Shah,et al.  A Model for Temperature Insensitive Trimmable MOSFET Current Sources , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[22]  Scott K. Arfin,et al.  Fast startup CMOS current references , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[23]  David Blaauw,et al.  A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[24]  Madhavan Swaminathan,et al.  A novel self-healing methodology for RF Amplifier circuits based on oscillation principles , 2012, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[25]  Dong Sam Ha,et al.  A compact resistorless 1.5-V CMOS current reference with 16.5-ppm/°C temperature coefficient , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[26]  Tetsuya Asai,et al.  A 1-$\mu\hbox{W}$ 600- $\hbox{ppm}/^{\circ}\hbox{C}$ Current Reference Circuit Consisting of Subthreshold CMOS Circuits , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[27]  Byung-Do Yang,et al.  An accurate current reference using temperature and process compensation current mirror , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[28]  Jan Doutreloigne,et al.  Comparative study on the effects of PVT variations between a novel all-MOS current reference and alternative CMOS solutions , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[29]  Mohamed I. Elmasry,et al.  On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB) , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  Zhihua Wang,et al.  A self-healing 2.4GHz LNA with on-chip S11/S21 measurement/calibration for in-situ PVT compensation , 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

[31]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[32]  Abhijit Chatterjee,et al.  A Power-Scalable Channel-Adaptive Wireless Receiver Based on Built-In Orthogonally Tunable LNA , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  Shanthi Pavan.  A fixed transconductance bias technique for CMOS analog integrated circuits , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[34]  Wei-Bin Yang,et al.  A 1.8-V 4.36-ppm/°C-TC bandgap reference with temperature variation calibration , 2013, 2013 International SoC Design Conference (ISOCC).

[35]  Jiann-Shiun Yuan,et al.  CMOS Transistor Amplifier Temperature Compensation: Modeling and Analysis , 2012, IEEE Transactions on Device and Materials Reliability.

[36]  Fengqi Yu,et al.  A Novel 1.2–V 4.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[37]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[38]  Melik Yazici,et al.  Wide Range, Process and Temperature Compensated Voltage Controlled Current Source , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[39]  Abhijit Chatterjee,et al.  Self-correcting, self-testing circuits and systems for post-manufacturing yield improvement , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[40]  Xuan Zhang,et al.  Process-Invariant Current Source Design: Methodology and Examples , 2007, IEEE Journal of Solid-State Circuits.

[41]  Franziska Hoffmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[42]  Liang-Hung Lu,et al.  A built-in gain calibration technique for RF low-noise amplifiers , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[43]  SeongHwan Cho,et al.  A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[44]  Jose-Luis Gonzalez Jimenez,et al.  Process and Temperature Compensation for RF Low-Noise Amplifiers and Mixers , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[45]  Johan Haanstra,et al.  Complementary constant-gm biasing of Nauta-transconductors in low-power gm-C filters to +/−2% accuracy over temperature , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

[46]  Trung-Kien Nguyen,et al.  CMOS low-noise amplifier design optimization techniques , 2004, IEEE Transactions on Microwave Theory and Techniques.

[47]  Yu-Jiu Wang,et al.  A PVT-Independent Constant- $G_{m}$ Bias Technique Based on Analog Computation , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.