Generalized Convolution Simulation Stack for RRAM Device based Deep Learning Neural Network

In this work, a generalized simulation software (HDL - Hardware Description Language) stack for convolution operation, used to analyze any RRAM device performance while plugged into a deep learning network, is constructed and simulated. This HDL software stack is a hardware abstracted matrix convolution implementation, used by RRAM device development engineers to quickly plug the device parameters into this framework and generate an application-level simulated prediction. The design output from this framework can be used to compute the area and power impact for any given end application based on the configuration, material and structure of the RRAM. A Verilog based HDL program is developed to build gate-level 32-bit floating-point adder and multiplier and in turn, these two arithmetic modules are connected hierarchically to perform configurable 1 × 1 to 11 × 11 (32-bit) parallel matrix computations used in the deep learning network.