Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays
暂无分享,去创建一个
Steven J. E. Wilton | Jeffrey B. Goeders | Al-Shahna Jamal | Eli Cahill | S. Wilton | Al-Shahna Jamal | Eli Cahill
[1] Jason Helge Anderson,et al. Source-level debugging for FPGA high-level synthesis , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).
[2] Philippe Coussy,et al. Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design , 2009, IEEE Des. Test Comput..
[3] Yu Ting Chen,et al. A Survey and Evaluation of FPGA High-Level Synthesis Tools , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Deming Chen,et al. Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only) , 2016, FPGA.
[5] Daniel Gajski,et al. Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.
[6] Deming Chen,et al. AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS , 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).
[7] Steven J. E. Wilton,et al. Effective FPGA debug for high-level synthesis generated circuits , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).
[8] Deming Chen,et al. Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation , 2016, DAC.
[9] Hiroyuki Tomiyama,et al. Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis , 2009, J. Inf. Process..
[10] Fabrizio Ferrandi,et al. Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis , 2017, ACM Trans. Embed. Comput. Syst..
[11] Brad L. Hutchings,et al. New approaches for in-system debug of behaviorally-synthesized FPGA circuits , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).
[12] Steven J. E. Wilton,et al. Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).
[13] Steven J. E. Wilton,et al. Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Fabrizio Ferrandi,et al. Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).
[15] Fabrizio Ferrandi,et al. Trace-based automated logical debugging for high-level synthesis generated circuits , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).
[16] Steven J. E. Wilton,et al. Architecture Exploration for HLS-Oriented FPGA Debug Overlays , 2018, FPGA.
[17] Brad L. Hutchings,et al. Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs , 2015, FPGA.
[18] Steven J. E. Wilton,et al. An adaptive virtual overlay for fast trigger insertion for FPGA debug , 2015, 2015 International Conference on Field Programmable Technology (FPT).
[19] Jason Helge Anderson,et al. LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems , 2013, TECS.
[20] Steven J. E. Wilton,et al. Allowing Software Developers to Debug HLS Hardware , 2015, ArXiv.
[21] Gu-Yeon Wei,et al. MachSuite: Benchmarks for accelerator design and customized architectures , 2014, 2014 IEEE International Symposium on Workload Characterization (IISWC).