A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing

A high-speed FIR filter structure is proposed in this paper by utilizing bit-segmentation adders and symmetric transpose 2-block FIR structure. First, a bit-segmented adder chain-based design is proposed with bit-segmentation adders. Second, a basic unit design of symmetric transpose block FIR is proposed to reduce the critical path delay. The evaluation results show that, when compared with state-of-the-art high-speed CSD multiplier-based FIR filter design, the proposed design requires 14.1% less area while provides 7.9% frequency improvement, 10.2% reduction of power consumption, 22.8% reduction of energy-delay-product and 20.4% reduction of area-delay-product, which shows the effectiveness of the proposed method.

[1]  Youhua Shi,et al.  Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[2]  Ming-Chih Chen,et al.  Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Basant K. Mohanty,et al.  A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Ya Jun Yu,et al.  Design of Low-Power Multiplierless Linear-Phase FIR Filters , 2017, IEEE Access.

[5]  Neha Goel,et al.  Design of FIR Filter Using FCSD Representation , 2015, 2015 IEEE International Conference on Computational Intelligence & Communication Technology.

[6]  Xin Lou,et al.  Low complexity and low power multiplierless FIR filter implementation , 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

[7]  Youhua Shi,et al.  A low cost and high speed CSD-based symmetric transpose block FIR implementation , 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

[8]  Jiajia Chen,et al.  Design of low complexity programmable FIR filters using multiplexers array optimization , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).