Star-Mesh NoC 반도체칩 설계를 위한 트랜잭션 수준 DEVS 형식론 기반 모델링 기법

This paper introduces a new modeling simulation methodology for NoC(Network-on-Chip) design in a transaction level based on a mathematical formalism called the DEVS (Discrete Event Systems Specification) formalism. This methodology can be used to verify architectural design prior to CAD engineering design to determine desirable parameters such as buffer size and latency of Star-mesh NoC topology as well as performance evaluation. The transaction level model of NoC in DEVS formalism can be simulated by using the simulation engine DEVSim++. This can be useful for architectural exploration of NoC before costly engineering design and fabrication.