论文信息 - A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz

A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz

A recent trend in cellular basestation design is to digitize multiple channels with a single ADC, often at the intermediate frequency (IF). This requires an ADC with wide dynamic range, particularly SFDR above 80 dB and SNR better than 70 dB, even when sampling input frequencies above 70 MHz. This 12b, 65MSample/s (MSPS) ADC incorporates a wide-bandwidth, low-distortion input stage coupled with a digitally-calibrated, multibit pipeline architecture optimized for low power consumption.

[1] Bang-Sup Song,et al. Digital-domain calibration of multistep analog-to-digital converters , 1992 .

[2] Paul R. Gray,et al. A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[3] L. Singer,et al. A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[4] Todd L. Brooks,et al. A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997 .

[5] P. R. Gray,et al. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[6] A 1 . 5V , 10-bit , 14 . 3-MS / s CMOS Pipeline Analog-to-Digital Converter , 1999 .