Parallel Turbo coder

Discloses a parallel Turbo encoder, comprising: the parallel interleaver, interleaving address generator comprises two interleaved and alternately serve as a buffer read buffer and write buffer, each buffer includes interleaving for storing respective bits plurality of memory cells, said plurality of memory cells in the interleaving address generator for under control of control signals generated by the respective bits, and outputs the parallel bit streams parallel systems interleaved bit stream; a first constituent encoder for parallel system parallel encoding bit stream, generating a first parity bit stream; and a second constituent encoder, interleaving the parallel stream is encoded, generating a second parity bit stream. The Turbo encoder of the embodiment of the present invention has a higher throughput and shorter wait time.