Modeling and simulation of real defects using fuzzy logic

Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the traditional zero-resistance model is not sufficient. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate-level. Our method produces more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test pattern statistics for the ISCAS85 benchmarks.

[1]  Melvin A. Breuer,et al.  SWiTEST: a switch level test generation system for CMOS combinational circuits , 1992, DAC '92.

[2]  Sudhakar M. Reddy,et al.  Fast Identification of Robust Dependent Path Delay Faults , 1995, 32nd Design Automation Conference.

[3]  Wojciech Maly,et al.  Physically realistic fault models for analog CMOS neural networks , 1991 .

[4]  Christos A. Papachristou,et al.  A scheme for integrated controller-datapath fault testing , 1997, DAC.

[5]  Janak H. Patel,et al.  Fast and accurate CMOS bridging fault simulation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[6]  Michele Favalli,et al.  Fault simulation of parametric bridging faults in CMOS IC's , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Robert C. Aitken.  Finding defects with fault models , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[8]  M. Nourani,et al.  A Scheme For Integrated Controller-datapath Fault Testing , 1997, Proceedings of the 34th Design Automation Conference.

[9]  Heinrich Theodor Vierhaus,et al.  CMOS bridges and resistive transistor faults: IDDQ versus delay effects , 1993, Proceedings of IEEE International Test Conference - (ITC).

[10]  Tracy Larrabee,et al.  Bridge Fault Simulation Strategies for CMOS Integrated Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[11]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[12]  Janak H. Patel,et al.  E-PROOFS: a CMOS bridging fault simulator , 1992, ICCAD.

[13]  John M. Acken,et al.  Fault Model Evolution For Diagnosis: Accuracy vs Precision , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[14]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[15]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[16]  Tracy Larrabee,et al.  Diagnosing realistic bridging faults with single stuck-at information , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Jochen A. G. Jess,et al.  An efficient CMOS bridging fault simulator: with SPICE accuracy , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Jürgen Alt,et al.  Simulation of non-classical faults on the gate level - The fault simulator COMSIM , 1993, Proceedings of IEEE International Test Conference - (ITC).

[19]  John F. Wakerly,et al.  Digital design - principles and practices , 1990, Prentice Hall Series in computer engineering.

[20]  E. Mizutani,et al.  Neuro-Fuzzy and Soft Computing-A Computational Approach to Learning and Machine Intelligence [Book Review] , 1997, IEEE Transactions on Automatic Control.

[21]  Janak H. Patel,et al.  E-PROOFS: A CMOS bridging fault simulator , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[22]  Prabhakar Goel,et al.  PODEM-X: An Automatic Test Generation System for VLSI Logic Structures , 1981, 18th Design Automation Conference.

[23]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[24]  Li-Xin Wang,et al.  A Course In Fuzzy Systems and Control , 1996 .

[25]  Anthony C. Miller.  I/sub DDQ/ testing in deep submicron integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).