Robust design and experimental demonstrations of carbon nanotube digital circuits

Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient digital systems. However, carbon nanotubes (CNTs) are inherently highly subject to imperfections and variations that pose major obstacles to the design of robust and very-large-scale CNFET digital systems. This paper presents an overview of imperfection-immune design and robust CNT processing techniques that enabled the demonstration of the first programmable microprocessor built using CNTs. We also present an overview of a systematic methodology that selects effective combinations of CNT processing options and CNFET circuit design techniques to overcome CNT variations.

[1]  Georges G. E. Gielen,et al.  Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Hai Wei,et al.  Carbon nanotube circuit integration up to sub-20 nm channel lengths. , 2014, ACS nano.

[3]  H.-S. Philip Wong,et al.  Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[5]  Subhasish Mitra,et al.  Monolithic three-dimensional integration of carbon nanotube FETs with silicon CMOS , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[6]  H. Wong,et al.  VLSI-compatible carbon nanotube doping technique with low work-function metal oxides. , 2014, Nano letters.

[7]  H. Wong,et al.  Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures , 2008, 2008 Symposium on VLSI Technology.

[8]  Yong-Bin Kim,et al.  Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems , 2010, IEEE Transactions on Instrumentation and Measurement.

[9]  Shekhar Y. Borkar.  3D integration for energy efficient system design , 2006, 2009 Symposium on VLSI Technology.

[10]  K. Roy,et al.  Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits , 2009, IEEE Transactions on Electron Devices.

[11]  Georges G. E. Gielen,et al.  Sacha: The stanford carbon nanotube controlled handshaking robot , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[12]  Hai Wei,et al.  Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits , 2010, 2010 Symposium on VLSI Technology.

[13]  Hai Wei,et al.  Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes , 2011, IEEE Transactions on Nanotechnology.

[14]  R. Krupke,et al.  Separation of Metallic from Semiconducting Single-Walled Carbon Nanotubes , 2003, Science.

[15]  Wilfried Haensch,et al.  Evaluation of field-effect mobility and contact resistance of transistors that use solution-processed single-walled carbon nanotubes. , 2012, ACS nano.

[16]  Hai Wei,et al.  Carbon Nanotube Robust Digital VLSI , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  S. Barman,et al.  Self-Sorted, Aligned Nanotube Networks for Thin-Film Transistors , 2008, Science.

[18]  Sheng Wang,et al.  Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V , 2012 .

[19]  Hong-Yu Chen,et al.  Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer , 2012, IEEE Transactions on Electron Devices.

[20]  Nishant Patil,et al.  Carbon Nanotube circuits in the presence of carbon nanotube density variations , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[21]  L. Qu,et al.  Preferential syntheses of semiconducting vertically aligned single-walled carbon nanotubes for direct use in FETs. , 2008, Nano letters.

[22]  P. Avouris,et al.  Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown , 2001, Science.

[23]  H. Wong,et al.  Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes , 2009, IEEE Transactions on Nanotechnology.

[24]  Jie Zhang,et al.  Overcoming carbon nanotube variations through co-optimized technology and circuit design , 2011, 2011 International Electron Devices Meeting.

[25]  H.-S. Philip Wong,et al.  Carbon nanotube computer , 2013, Nature.

[26]  A. Rinzler,et al.  An Integrated Logic Circuit Assembled on a Single Carbon Nanotube , 2006, Science.

[27]  H.-S. Philip Wong,et al.  Performance benchmarks for Si, III–V, TFET, and carbon nanotube FET - re-thinking the technology assessment methodology for complementary logic applications , 2010, 2010 International Electron Devices Meeting.

[28]  Hai Wei,et al.  Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[29]  Hai Wei,et al.  Rapid exploration of processing and design guidelines to overcome carbon nanotube variations , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[30]  W. Haensch,et al.  High-density integration of carbon nanotubes via chemical self-assembly. , 2012, Nature nanotechnology.

[31]  Giovanni De Micheli,et al.  Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement , 2010, Design Automation Conference.

[32]  Giovanni De Micheli,et al.  Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[33]  Mark C. Hersam,et al.  Sorting carbon nanotubes by electronic structure using density differentiation , 2006, Nature nanotechnology.

[34]  S. Bachilo,et al.  Advanced sorting of single-walled carbon nanotubes by nonlinear density-gradient ultracentrifugation. , 2010, Nature nanotechnology.

[35]  Jörg Appenzeller,et al.  Carbon Nanotubes for High-Performance Electronics—Progress and Prospect , 2008, Proceedings of the IEEE.

[36]  Hai Wei,et al.  VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[37]  H.-S. Philip Wong,et al.  First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier , 2006, 2006 International Electron Devices Meeting.

[38]  Nishant Patil,et al.  Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[39]  Hai Wei,et al.  Monolithic three-dimensional integration of carbon nanotube FET complementary logic circuits , 2013, 2013 IEEE International Electron Devices Meeting.

[40]  T. Ebbesen.  Physical Properties of Carbon Nanotubes , 1997 .

[41]  W. Paul,et al.  Computer Architecture , 2000, Springer Berlin Heidelberg.

[42]  T. Numata,et al.  Understanding of short-channel mobility in tri-gate nanowire MOSFETs and enhanced stress memorization technique for performance improvement , 2010, 2010 International Electron Devices Meeting.

[43]  J. Rogers,et al.  Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates , 2008, Nature.

[44]  H.-S. Philip Wong,et al.  A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[45]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, ISCA 2001.

[46]  Chris C. N. Chu.  FLUTE: fast lookup table based wirelength estimation technique , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[47]  Sarunya Bangsaruntip,et al.  Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs , 2010, IEEE Electron Device Letters.

[48]  Mehdi Baradaran Tahoori,et al.  Application-independent defect tolerance of reconfigurable nanoarchitectures , 2006, JETC.

[49]  Jie Deng,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking , 2007, IEEE Transactions on Electron Devices.

[50]  Hai Wei,et al.  Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs , 2014, IEEE Journal of Solid-State Circuits.

[51]  Jarrod A. Roy,et al.  High-Performance Routing at the Nanometer Scale , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[52]  H.-S. Philip Wong,et al.  Increasing the semiconducting fraction in ensembles of single-walled carbon nanotubes , 2012 .

[53]  Sheng Wang,et al.  CMOS-based carbon nanotube pass-transistor logic integrated circuits , 2012, Nature Communications.

[54]  André DeHon,et al.  Seven strategies for tolerating highly defective fabrication , 2005, IEEE Design & Test of Computers.

[55]  P. Kidwell,et al.  The universal turing machine: a half-century survey , 1996, IEEE Annals of the History of Computing.

[56]  Hai Wei,et al.  Linear increases in carbon nanotube density through multiple transfer technique. , 2011, Nano letters.

[57]  H. Wong,et al.  Impact of a Process Variation on Nanowire and Nanotube Device Performance , 2007, IEEE Transactions on Electron Devices.

[58]  J. Rogers,et al.  High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. , 2007, Nature nanotechnology.

[59]  Mark S. Lundstrom,et al.  Sub-10 nm carbon nanotube transistor , 2011, 2011 International Electron Devices Meeting.

[60]  H.-S. Philip Wong,et al.  Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[61]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[62]  Hai Wei,et al.  ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration , 2009, IEEE Transactions on Electron Devices.

[63]  J. Mazurier,et al.  Advances, challenges and opportunities in 3D CMOS sequential integration , 2011, 2011 International Electron Devices Meeting.