Optical Routing for 3-D System-On-Package

In this paper, we present the first optical router for 3-D system-on-package (SOP). Recent advances in optical device integration for SOP offer drastic advantages over electrical interconnects. We propose efficient algorithms for the construction of timing and congestion-driven waveguides taking into account the optical resource constraints. Our experimental results suggest that smart placement of waveguides coupled with other routing techniques can reduce electrical wirelength by 11% and improve performance by 23%, when a single optical layer is introduced for every placement layer.

[1]  Abhijit Chatterjee,et al.  Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages , 2004, GLSVLSI '04.

[2]  R.R. Tummala,et al.  SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade , 2004, IEEE Transactions on Advanced Packaging.

[3]  Yici Cai,et al.  Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[4]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[5]  Sung Kyu Lim,et al.  Placement and Routing for 3-D System-On-Package Designs , 2006, IEEE Transactions on Components and Packaging Technologies.

[6]  Jason Cong,et al.  Interconnect design for deep submicron ICs , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[7]  R.R. Tummala,et al.  Chip-to-chip optoelectronics SOP on organic boards or packages , 2004, IEEE Transactions on Advanced Packaging.

[8]  M. Michael Yovanovich,et al.  Analysis of thermal vias in high density interconnect technology , 1992, [1992 Proceedings] Eighth Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[9]  Michael Pecht,et al.  IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES BOARD OF GOVERNORS (Continued on back cover) , 2005 .

[10]  Frank K. Hwang,et al.  The rectilinear steiner arborescence problem , 2005, Algorithmica.

[11]  Kaustav Banerjee,et al.  Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu interconnects , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[12]  R. S. Li.  Optimization of thermal via design parameters based on an analytical thermal resistance model , 1998, ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208).

[13]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[14]  Abhijit Chatterjee,et al.  Physical design of optoelectronic system-on-a-package: a CAD tool and algorithms , 2005, Sixth international symposium on quality electronic design (isqed'05).