Efficient signed-digit-to-canonical-signed-digit recoding circuits

In this study, we propose a new signed-digit-to-canonical-signed-digit recoding circuit based on parallel prefix structures. Several articles have been devoted to the study of canonical signed-digit recoding circuits. However, most of those re-code from 2's complement binary number representation. Unlike those, our proposed architectures convert from signed-digit number representation. The circuit structure is somewhat different from those in previous articles, because each digit in the input is accompanied by its sign. We evaluate the proposed circuit and compare it with a circuit based on the conditional sum structure. We show that the proposed architectures performs faster by 30% or more than the circuit based on the conditional sum structure.

[1]  Elizabeth Elias,et al.  Design of frequency response masking FIR filter in the Canonic Signed Digit space using modified Artificial Bee Colony algorithm , 2013, Eng. Appl. Artif. Intell..

[2]  Xinming Huang,et al.  CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups , 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[3]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[4]  Akhilesh Tyagi,et al.  A Reduced-Area Scheme for Carry-Select Adders , 1993, IEEE Trans. Computers.

[5]  Majid Ahmadi,et al.  Application of neural networks with CSD coefficients for human face recognition , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[6]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[7]  Kyung-Ju Cho,et al.  Constant multiplier design using specialized bit pattern adders , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[8]  Evangelos Vassalos,et al.  CSD-RNS-based Single Constant Multipliers , 2012, J. Signal Process. Syst..

[9]  Sejung Yang,et al.  Efficient transform using canonical signed digit in reversible color transforms , 2009, J. Electronic Imaging.

[10]  Debajyoti Misra,et al.  Quadrature Mirror Filter bank with canonical signed digit representation using linear optimization algorithm , 2015, Proceedings of the 2015 Third International Conference on Computer, Communication, Control and Information Technology (C3IT).

[11]  A. Herrfeld,et al.  Look-ahead circuit for CSD-code carry determination , 1995 .

[12]  An-Yeu Wu,et al.  A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach , 2002 .

[13]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..

[14]  Sajal K. Das,et al.  Fast VLSI circuits for CSD coding and GNAF coding , 1996 .

[15]  Dayong Zhou,et al.  Iterative Radix-8 Multiplier Structure Based on a Novel Real-time CSD Recoding , 2007, 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers.

[16]  Gustavo A. Ruiz,et al.  Efficient canonic signed digit recoding , 2011, Microelectron. J..

[17]  Çetin Kaya Koç.  Parallel canonical recoding , 1996 .

[18]  Lei Chen,et al.  Improved multiplier of CSD used in digital signal processing , 2008, 2008 International Conference on Machine Learning and Cybernetics.

[19]  A. Willson,et al.  A programmable FIR digital filter using CSD coefficients , 1996 .

[20]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[21]  Neha Goel,et al.  Design of FIR Filter Using FCSD Representation , 2015, 2015 IEEE International Conference on Computational Intelligence & Communication Technology.