BigBus: A Scalable Optical Interconnect

This article presents BigBus, a novel design of an on-chip photonic network for a 1,024-node system. For such a large on-chip network, performance and power reduction are two mutually conflicting goals. This article uses a combination of strategies to reduce static power consumption while simultaneously improving performance and the energy-delay2 (ED2) product. The crux of the article is to segment the entire system into smaller clusters of nodes and adopt a hybrid strategy for each segment that includes conventional laser modulation, as well as a novel technique for sharing power across nodes dynamically. We represent energy internally as tokens, where one token will allow a node to send a message to any other node in its cluster. We allow optical stations to arbitrate for tokens at a global level, and then we predict the number of token equivalents of power that the off-chip laser needs to generate. Using these techniques, BigBus outperforms other competing proposals. We demonstrate a speedup of 14--34% over state of the art proposals and a 20--61% reduction in ED2.

[1]  Venkatesh Akella,et al.  Addressing system-level trimming issues in on-chip nanophotonic networks , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[2]  Yu Zhang,et al.  Firefly: illuminating future network-on-chip with nanophotonics , 2009, ISCA '09.

[3]  Smruti R. Sarangi,et al.  ColdBus: A Near-Optimal Power Efficient Optical Bus , 2015, 2015 IEEE 22nd International Conference on High Performance Computing (HiPC).

[4]  Avinash Karanth Kodi,et al.  Extending the Performance and Energy-Efficiency of Shared Memory Multicores with Nanophotonic Technology , 2014, IEEE Transactions on Parallel and Distributed Systems.

[5]  Mikko H. Lipasti,et al.  Light speed arbitration and flow control for nanophotonic interconnects , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[6]  Roberto Proietti,et al.  Scalable and distributed optical interconnect architecture based on AWGR for HPC and data centers , 2014, OFC 2014.

[7]  Sudeep Pasricha,et al.  OPAL: A multi-layer hybrid photonic NoC for 3D ICs , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[8]  Prathmesh Kallurkar,et al.  Tejas: A java based versatile micro-architectural simulator , 2015, 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[9]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[10]  Sudeep Pasricha,et al.  Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers , 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[11]  Xi Chen,et al.  HERMES: A Hierarchical Broadcast-Based Silicon Photonic Interconnect for Scalable Many-Core Systems , 2014, ArXiv.

[12]  Kevin Skadron,et al.  HotSpot 6.0: Validation, Acceleration and Extension , 2015 .

[13]  M. Lipson,et al.  High-Performance Silicon-Nitride-Based Multiple-Wavelength Source , 2011, IEEE Photonics Technology Letters.

[14]  Geoff V. Merrett.  PRiME: Power-efficient Reliable Many-core Embedded systems , 2018 .

[15]  Huaxi Gu,et al.  Design of 3D Optical Network on Chip , 2009, 2009 Symposium on Photonics and Optoelectronics.

[16]  Roberto Proietti,et al.  Scalable and high performance HPC architecture with optical interconnects , 2014, 2014 IEEE Photonics Conference.

[17]  Andrew B. Kahng,et al.  ORION 2.0: A Power-Area Simulator for Interconnection Networks , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  K. Bergman,et al.  Resolving the thermal challenges for silicon microring resonator devices , 2014 .

[19]  A. Enard,et al.  High Optical Power, High Gain and High Dynamic Range Directly Modulated Optical Link , 2013, Journal of Lightwave Technology.

[20]  Arvind Kumar,et al.  Three-dimensional integrated circuits , 2006, IBM J. Res. Dev..

[21]  Mikko H. Lipasti,et al.  Wavelength stealing: An opportunistic approach to channel sharing in multi-chip photonic interconnects , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[22]  Graham T. Reed,et al.  Silicon Photonics: The State of the Art , 2008 .

[23]  William J. Dally,et al.  Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.

[24]  José L. Abellán,et al.  Electro-Photonic NoC Designs for Kilocore Systems , 2016, ACM J. Emerg. Technol. Comput. Syst..

[25]  Xiaowen Wu,et al.  SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor , 2014, JETC.

[26]  Christopher Batten,et al.  Silicon-photonic clos networks for global on-chip communication , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[27]  George Kurian,et al.  ATAC: A 1000-core cache-coherent processor with on-chip optical network , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[28]  Smruti R. Sarangi,et al.  NUPLet: A Photonic Based Multi-Chip NUCA Architecture , 2017, 2017 IEEE International Conference on Computer Design (ICCD).

[29]  Rami G. Melhem,et al.  Channel borrowing: an energy-efficient nanophotonic crossbar architecture with light-weight arbitration , 2012, ICS '12.

[30]  M. Humphrey.  Calculation of coupling between tapered fiber modes and whispering-gallery modes of a spherical microlaser , 2004 .

[31]  Smruti R. Sarangi,et al.  Active microring based tunable optical power splitters , 2016 .

[32]  High-performance silicon-based multiple wavelength source , 2011, CLEO: 2011 - Laser Science to Photonic Applications.

[33]  Wei Zhang,et al.  3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  Pavel Borodulin,et al.  An 8-bit carry look-ahead adder with 150 ps latency and sub-microwatt power dissipation at 10 GHz , 2012, 1212.2994.

[35]  L. Chrostowski,et al.  Wavelength tuning and stabilization of microring-based filters using silicon in-resonator photoconductive heaters. , 2015, Optics express.

[36]  Li Zhou,et al.  PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[37]  Chao Chen,et al.  Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture , 2013, IEEE Journal of Selected Topics in Quantum Electronics.

[38]  Ahmed Louri,et al.  OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures , 2015, 2015 IEEE 23rd Annual Symposium on High-Performance Interconnects.

[39]  Sudeep Pasricha,et al.  SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast-Enabled Channel Sharing for Multicore Architectures , 2017, ACM J. Emerg. Technol. Comput. Syst..

[40]  Christopher Batten,et al.  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[41]  Smruti R. Sarangi,et al.  Optical overlay NUCA: A high speed substrate for shared L2 caches , 2014, 2014 21st International Conference on High Performance Computing (HiPC).

[42]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[43]  Yuan Xie,et al.  3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC) , 2009, 2009 IEEE International Conference on 3D System Integration.

[44]  Kevin Skadron,et al.  Scaling with Design Constraints: Predicting the Future of Big Chips , 2011, IEEE Micro.

[45]  Smruti R. Sarangi,et al.  OptiKit : An Open Source Kit for Simulation of On-Chip Optical Components , 2013 .

[46]  Smruti R. Sarangi,et al.  Optimal Power Efficient Photonic SWMR Buses , 2015, 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing.

[47]  José F. Martínez,et al.  A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing , 2010, ASPLOS XV.

[48]  John Kim,et al.  FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[49]  Roberto Proietti,et al.  AWGR-based all-to-all optical interconnects using limited number of wavelengths , 2013, 2013 Optical Interconnects Conference.

[50]  Ian O'Connor,et al.  Optical solutions for system-level interconnect , 2004, SLIP '04.

[51]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[52]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[53]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[54]  Nikolaos Hardavellas,et al.  EcoLaser: An adaptive laser control for energy-efficient on-chip photonic interconnects , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).