A harmonic rejection mixer in wideband transmitter

This paper proposes a novel harmonic rejection mixer (HRM) designed for wideband transmitter. The HRM was designed and simulated in 0.13um CMOS technology. The 3rd and 5th order harmonics are suppressed more than 30dB up to 1GHz operational frequency. The LO attenuation is more than 100dBc. Input P1dB is higher than 11dBm. Core circuit consumes negligible power consumption.

[1]  Eric A. M. Klumperink,et al.  A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  K. Folkesson,et al.  A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[3]  A.A. Abidi,et al.  The Path to the Software-Defined Radio Receiver , 2007, IEEE Journal of Solid-State Circuits.

[4]  Li Lin,et al.  A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  H. Pekau,et al.  A 2.4 GHz CMOS sub-sampling mixer with integrated filtering , 2005, IEEE Journal of Solid-State Circuits.