Reconfigurable SIMD massively parallel computers

This paper is a brief introduction to a new class of computers, the reconfigurable massively parallel computer. Its most distinguishing feature is the utilization of the reconfigurability of the interconnection network to establish a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved, and to remove faulty processors from the network so that the system operation can be kept uninterrupted while maintaining the same or slightly degraded efficiency. Several existing reconfigurable single instruction multiple data (SIMD) parallel architectures and their reconfiguration mechanism are described, the effectiveness of algorithm mapping, through reconfiguration, is demonstrated, and fault-tolerant schemes via reconfiguration are discussed. >

[1]  Quentin F. Stout,et al.  Hypercube message routing in the presence of faults , 1988, C3P.

[2]  Graham R. Nudd,et al.  Three-dimensional VLSI architecture for image understanding , 1985, J. Parallel Distributed Comput..

[3]  D. H. Schaefer,et al.  The GAM pyramid , 1987 .

[4]  T. J. Fountain.  Introducing local autonomy to processor arrays , 1988 .

[5]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[6]  Israel Koren.  A reconfigurable and fault-tolerant VLSI multiprocessor array , 1981, ISCA '81.

[7]  Theodosios Pavlidis,et al.  A hierarchical data structure for picture processing , 1975 .

[8]  S. Y. Kung,et al.  Yield enhancement for WSI array processors using two-and-half-track switches , 1990, 1990 Proceedings. International Conference on Wafer Scale Integration.

[9]  H. Li,et al.  Sparse matrix vector multiplication on polymorphic-torus , 1988, Proceedings., 2nd Symposium on the Frontiers of Massively Parallel Computation.

[10]  Michael J. Flynn,et al.  Some Computer Organizations and Their Effectiveness , 1972, IEEE Transactions on Computers.

[11]  Massimo Maresca,et al.  Polymorphic-Torus Network , 1989, IEEE Trans. Computers.

[12]  Kenneth E. Batcher,et al.  Design of a Massively Parallel Processor , 1980, IEEE Transactions on Computers.

[13]  T. Sudo,et al.  An LSI adaptive array processor , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[14]  M.J.B. Duff,et al.  PARALLEL PROCESSING PATTERN RECOGNITION SYSTEM UCPR1. , 1967 .

[15]  Svetlana P. Kartashev,et al.  Reconfigurable multicomputer networks for very fast real-time applications , 1899, AFIPS '82.

[16]  Jerome Rothstein.  Bus automata, brains, and mental models , 1988, IEEE Trans. Syst. Man Cybern..

[17]  S. H. Unger,et al.  A Computer Oriented toward Spatial Problems , 1899, Proceedings of the IRE.

[18]  Jake K. Aggarwal,et al.  Reconfiguration Strategies for Parallel Architectures , 1985, Computer.

[19]  Renato Stefanelli,et al.  PAPIA: Pyramidal architecture for parallel image analysis , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[20]  Lawrence Snyder,et al.  Introduction to the configurable, highly parallel computer , 1982, Computer.

[21]  Massimo Maresca,et al.  Polymorphic-Torus Architecture for Computer Vision , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[22]  Renato Stefanelli,et al.  Reconfigurable architectures for VLSI processing arrays , 1986 .

[23]  Richard M. Brown,et al.  The ILLIAC IV Computer , 1968, IEEE Transactions on Computers.

[24]  José A. B. Fortes,et al.  A taxonomy of reconfiguration techniques for fault-tolerant processor arrays , 1990, Computer.

[25]  W.R. Moore,et al.  A review of fault-tolerant techniques for the enhancement of integrated circuit yield , 1986, Proceedings of the IEEE.

[26]  M. Maresca,et al.  Parallel architectures for vision , 1988 .

[27]  Hungwen Li,et al.  Connection Autonomy in SIMD Computers: A VLSI Implementation , 1989, J. Parallel Distributed Comput..

[28]  David B. Shu,et al.  The Gated Interconnection Network for Dynamic Programming , 1988 .

[29]  Chi-Jen Lu,et al.  Constant Time Algorithms for the Transitive Closure Problem and Its Applications , 1990, ICPP.

[30]  T. J. Fountain,et al.  A cellular logic array for image processing , 1973, Pattern Recognit..

[31]  Dionysios I. Reisis,et al.  Image computations on reconfigurable VLSI arrays , 1988, Proceedings CVPR '88: The Computer Society Conference on Computer Vision and Pattern Recognition.

[32]  Quentin F. Stout.  Using clerk in parallel processing , 1982, FOCS 1982.

[33]  Charles C. Weems,et al.  Image understanding architecture and applications , 1988 .

[34]  Quentin F. Stout.  Using clerk in parallel processing , 1982, 23rd Annual Symposium on Foundations of Computer Science (sfcs 1982).

[35]  Manfred Glesner,et al.  Defect Tolerance in a Wafer Scale Array for Image Processing , 1989 .