Network on chip simulations for benchmarking

Networks are becoming increasingly popular for use as on-chip interconnects. The problems with specification and performance evaluation increase with these solutions compared to the traditional interconnect. This paper describes the design and simulation environment developed in the SoCBUS network-on-chip project. This environment is used as a basis to develop the benchmarking procedures necessary to assess the performance of the networks. Two benchmarking examples are presented and used for evaluation of the SoCBUS network. These examples show how the simulation environment can be used to find the load bottleneck. They also show the appropriateness of the SoCBUS solution for (hard) real-time systems.

[1]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[2]  Kees G. W. Goossens,et al.  Cost-performance trade-offs in networks on chip: a simulation-based approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Daniel Wiklund.  An on-chip network architecture for hard real time systems , 2003 .

[4]  Dake Liu,et al.  Design of a switching node (router) for on-chip networks , 2003, ASIC, 2003. Proceedings. 5th International Conference on.

[5]  Kees G. W. Goossens,et al.  Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[6]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  Dake Liu,et al.  Design of a system-on-chip switched network and its design support , 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.