A Design of Digital Logic Analyzer Based on DSP and CPLD

The digital logic analyzer is mainly used to analyze a set of logic signal waveforms in a digital system,and to show the logic relationship among them.In this paper,we use a Digital Signal Processor (DSP)to sample the eight channel digital signals,a CPLD to control the oscilloscope′s input electric circuit,and a dualport RAM to coordinate the data transformation between DSP and CPLD.The signals is sampled in the typical time segment according to the specified triggering condition.A state machine with 28 states is designed in the CPLD to realize the digital channel display,time line display and trigging position display.It is convenient to analyze the logic relationships among the 8 digital signals,as they are displayed on the oscilloscope′s screen at the same time.This design can sample digital signals with the frequency up to 1 MHz.It allows users to set a 1~3 triggering condition levels.A further function development is allowed,too.All the above conforms this design to the need in digital system experiments and digital circuit design.This paper labors the software and hardware design and realization of this system.