The highest speed silicon logic chips are currently made using the emitter coupled logic (ECL) bipolar technology which inherently dissipates more power than other logic families. Recent developments include a macrocell array (MCA 2TM) logic chip dissipating up to 12 W of power over 0.47 cm2and there are plans to develop a technology chip dissipating 10 W of power over an area of 1.03 cm2, both to be used in high performance applications. It is essential that the packages housing these chips, have good thermal and electrical characteristics to fully realize the potential of these chips. Extensive computer-based thermal modeling and experimental studies were performed to design a high thermal performance ceramic pin array package utilizing the cavity down approach. Single-layer alumina, muitilayer alumina, and muitilayer beryllia-alumina composite packages were studied. Both unidirectional and omnidirectional heatsinks were computer modeled, designed, and tested in a wind tunnel. Power transistor and MCA 2 logic chips were used to simulate the power levels. Both parametric and infrared microscopic methods were used to determine the junction temperatures. Finite difference modeling calculations were performed for various package configurations and compared with experimental results. The work has resulted in packages meeting the thermal requirements. A beryllia-alumina composite substrate package with an omnidirectional heatsink is chosen to house the 12 W power dissipating MCA 2 chip. It has a measured value of 3.3°C/W for Theta ja in 750 linear feet per minute (3.8 m/s) air flow at sea level. An all alumina substrate pin array package with an omnidirectional heatsink is chosen as the technology package to house the 10 W power chip. It has a measured value of 5.1°C/W for Theta ja in 1000 lfm (5.1 m/s) air flow at sea level.