Modeling Energy Dissipation in Low Power Caches

Modern microprocessors employ one or two levels of on–chip caches that are implemented using static RAM and take up a large portion of the Silicon real estate, consuming a significant amount of power. We present detailed analytical models for estimating the energy dissipated in conventionally–organized caches as well as caches that are organized to have reduced energy dissipations. We also validate the accuracy of these analytical models by comparing the analytically obtained power dissipations with the dissipations obtained using a detailed simulator called CAPE (CAache Power Estimator) for the simulated execution of many SPEC 95 benchmarks. Our analytical models for the energy dissipation in caches use counts for hits, misses, as well as the number of reads and writes, which are obtained from an architectural simulator, and assumes transitions due to the actual values of the address and data bits to be stochastically distributed. We show that the analytical models for conventional caches estimate the overall power dissipation within less than 10% error (compared to the energy estimated from actual transition counts). On the average, the analytical model overpredict the energy dissipations by about 3% to 15%. However, for some of the energy efficient cache organizations, the analytical model over–predict the energy dissipations by as much as 20%. We compare the results of our analysis with actual transition–count based power estimations obtained from CAPE to show that the inaccuracies in the analytical models are due to correlated transitions, a factor that actually plays a significant role in making some cache organizations energy efficient.

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