An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems

Recovering the symbols in a multiple-input multiple-output (MIMO) receiver is a computationally intensive process. The layered space-time (LST) algorithms provide a reasonable tradeoff between complexity and performance. Commercial digital signal processors (DSPs) have become a key component in many high-volume products such as cellular telephones. As an alternative to power-hungry DSPs, we propose to use a moderately parallel single-instruction stream, multiple-data stream (SIMD) coprocessor architecture, called DSP-RAM, to implement an LST MIMO receiver that offers high performance with relatively low power consumption. For a typical indoor wireless environment, a 100-MHz DSP-RAM can potentially provide more than ten times greater decoding throughput at the receiver of a (4,4) MIMO system compared with a conventional 720-MHz DSP. The DSP-RAM processor has been coded in a hardware description language (HDL) and synthesized for both available field-programmable gate arrays (FPGAs) and for a 0.18-mum CMOS standard cell implementation

[1]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[2]  Babak Hassibi,et al.  An efficient square-root algorithm for BLAST , 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

[3]  Zhan Guo,et al.  A low-complexity VLSI architecture for square root MIMO detection , 2003 .

[4]  Milos D. Ercegovac,et al.  Digital Arithmetic , 2003, Wiley Encyclopedia of Computer Science and Engineering.

[5]  Rohit U. Nabar,et al.  Introduction to Space-Time Wireless Communications , 2003 .

[6]  Jacob Benesty,et al.  A fast recursive algorithm for optimum sequential signal detection in a BLAST system , 2003, IEEE Trans. Signal Process..

[7]  Thomas L. Marzetta,et al.  BLAST training : Estimating Channel Characteristics for High-Capacity Space-Time Wireless , 1999 .

[8]  Narayan B. Mandayam,et al.  DIMACS Series in Discrete Mathematics and Theoretical Computer Science Pilot Assisted Estimation of MIMO Fading Channel Response and Achievable Data Rates , 2022 .

[9]  D. Garrett,et al.  A 28.8 Mb/s 4/spl times/4 MIMO 3G high-speed downlink packet access receiver with normalized least mean square equalization , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[10]  John N. Tsitsiklis,et al.  Parallel and distributed computation , 1989 .

[11]  Bruce F. Cockburn,et al.  Implementation of DSP-RAM: an architecture for parallel digital signal processing in memory , 2001, Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555).

[12]  Ashutosh Sabharwal,et al.  An FPGA based rapid prototyping platform for MIMO systems , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[13]  Bruce F. Cockburn,et al.  Parallel filtering and thresholding of images on the SIMD DSP-RAM architecture , 2002, IEEE CCECE2002. Canadian Conference on Electrical and Computer Engineering. Conference Proceedings (Cat. No.02CH37373).

[14]  B. Hassibi,et al.  On the expected complexity of sphere decoding , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[15]  Junqiang Sun,et al.  Tms320c6000 cpu and instruction set reference guide , 2000 .

[16]  M. J. Gans,et al.  On Limits of Wireless Communications in a Fading Environment when Using Multiple Antennas , 1998, Wirel. Pers. Commun..

[17]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[18]  K. Kammeyer,et al.  Efficient algorithm for decoding layered space-time codes , 2001 .

[19]  Theodore S. Rappaport,et al.  Wireless communications - principles and practice , 1996 .

[20]  J. Rinas,et al.  Efficient Algorithm for Detecting Layered Space-Time Codes , 2002 .

[21]  Maya Gokhale,et al.  Processing in Memory: The Terasys Massively Parallel PIM Array , 1995, Computer.

[22]  François Gagnon,et al.  Performance analysis of the V-BLAST algorithm: an analytical approach , 2004, IEEE Transactions on Wireless Communications.

[23]  Zhan Guo,et al.  A VLSI implementation of MIMO detection for future wireless communications , 2003, 14th IEEE Proceedings on Personal, Indoor and Mobile Radio Communications, 2003. PIMRC 2003..

[24]  Reinaldo A. Valenzuela,et al.  Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture , 1999 .

[25]  Markus Rupp,et al.  Prototype experience for MIMO BLAST over third-generation wireless system , 2003, IEEE J. Sel. Areas Commun..

[26]  Markus Rupp,et al.  FPGA implementation of a MIMO receiver front-end for the UMTS downlink , 2002, 2002 International Zurich Seminar on Broadband Communications Access - Transmission - Networking (Cat. No.02TH8599).