Design of a single event upset (SEU) mitigation technique for programmable devices

This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for reconfigurable architectures. The proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. The result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes

[1]  E. Normand.  Single event upset at ground level , 1996 .

[2]  Luigi Carro,et al.  Designing Fault Tolerant Systems into SRAM-based , 2003 .

[3]  P. Dyreklev,et al.  In-flight and ground testing of single event upset sensitivity in static RAMs , 1997, RADECS 97. Fourth European Conference on Radiation and its Effects on Components and Systems (Cat. No.97TH8294).

[4]  C. Carmichael,et al.  A fault injection analysis of Virtex FPGA TMR design methodology , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[5]  Michael Nicolaidis,et al.  Embedded robustness IPs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Daniela De Venuto,et al.  International Symposium on Quality Electronic Design , 2005, Microelectron. J..

[7]  K. Johansson,et al.  In-flight and ground testing of single event upset sensitivity in static RAMs , 1997 .

[8]  J. Olsen,et al.  Neutron-induced single event upsets in static RAMS observed a 10 km flight attitude , 1993 .

[9]  C. Carmichael,et al.  Proton Testing of SEU Mitigation Methods for the Virtex FPGA , 2001 .